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Commit f42826d

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Stop adding to PtrB
1 parent d4d5ca1 commit f42826d

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3 files changed

+753
-486
lines changed

3 files changed

+753
-486
lines changed

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1617,22 +1617,20 @@ void DAGTypeLegalizer::SplitVecRes_BITCAST(SDNode *N, SDValue &Lo,
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void DAGTypeLegalizer::SplitVecRes_LOOP_DEPENDENCE_MASK(SDNode *N, SDValue &Lo,
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SDValue &Hi) {
1620-
unsigned EltSize = N->getConstantOperandVal(2);
1621-
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SDLoc DL(N);
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EVT LoVT, HiVT;
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std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
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SDValue PtrA = N->getOperand(0);
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SDValue PtrB = N->getOperand(1);
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Lo = DAG.getNode(N->getOpcode(), DL, LoVT, PtrA, PtrB, N->getOperand(2));
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1627+
unsigned EltSize = N->getConstantOperandVal(2);
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unsigned Offset = EltSize * HiVT.getVectorMinNumElements();
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SDValue Addend = HiVT.isScalableVT()
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? DAG.getVScale(DL, MVT::i64, APInt(64, Offset))
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: DAG.getConstant(Offset, DL, MVT::i64);
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PtrA = DAG.getNode(ISD::ADD, DL, MVT::i64, PtrA, Addend);
1635-
PtrB = DAG.getNode(ISD::ADD, DL, MVT::i64, PtrB, Addend);
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Hi = DAG.getNode(N->getOpcode(), DL, HiVT, PtrA, PtrB, N->getOperand(2));
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}
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