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[AMDGPU] Replace unsigned with Register in SIMachineScheduler. NFC
Some of these may eventually need to VirtRegOrUnit.
1 parent 37fdde6 commit f46eb14

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2 files changed

+37
-40
lines changed

2 files changed

+37
-40
lines changed

‎llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp‎

Lines changed: 24 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -284,10 +284,9 @@ void SIScheduleBlock::fastSchedule() {
284284
}
285285

286286
// Returns if the register was set between first and last.
287-
static bool isDefBetween(unsigned Reg,
288-
SlotIndex First, SlotIndex Last,
289-
const MachineRegisterInfo *MRI,
290-
const LiveIntervals *LIS) {
287+
static bool isDefBetween(Register Reg, SlotIndex First, SlotIndex Last,
288+
const MachineRegisterInfo *MRI,
289+
const LiveIntervals *LIS) {
291290
for (MachineRegisterInfo::def_instr_iterator
292291
UI = MRI->def_instr_begin(Reg),
293292
UE = MRI->def_instr_end(); UI != UE; ++UI) {
@@ -581,11 +580,11 @@ void SIScheduleBlock::printDebug(bool full) {
581580
<< LiveOutPressure[AMDGPU::RegisterPressureSets::SReg_32] << ' '
582581
<< LiveOutPressure[AMDGPU::RegisterPressureSets::VGPR_32] << "\n\n";
583582
dbgs() << "LiveIns:\n";
584-
for (unsigned Reg : LiveInRegs)
583+
for (Register Reg : LiveInRegs)
585584
dbgs() << printVRegOrUnit(Reg, DAG->getTRI()) << ' ';
586585

587586
dbgs() << "\nLiveOuts:\n";
588-
for (unsigned Reg : LiveOutRegs)
587+
for (Register Reg : LiveOutRegs)
589588
dbgs() << printVRegOrUnit(Reg, DAG->getTRI()) << ' ';
590589
}
591590

@@ -1413,12 +1412,12 @@ SIScheduleBlockScheduler::SIScheduleBlockScheduler(SIScheduleDAGMI *DAG,
14131412
// highest topological index.
14141413
LiveOutRegsNumUsages.resize(Blocks.size());
14151414
for (SIScheduleBlock *Block : Blocks) {
1416-
for (unsigned Reg : Block->getInRegs()) {
1415+
for (Register Reg : Block->getInRegs()) {
14171416
bool Found = false;
14181417
int topoInd = -1;
14191418
for (SIScheduleBlock* Pred: Block->getPreds()) {
1420-
std::set<unsigned> PredOutRegs = Pred->getOutRegs();
1421-
std::set<unsigned>::iterator RegPos = PredOutRegs.find(Reg);
1419+
std::set<Register> PredOutRegs = Pred->getOutRegs();
1420+
std::set<Register>::iterator RegPos = PredOutRegs.find(Reg);
14221421

14231422
if (RegPos != PredOutRegs.end()) {
14241423
Found = true;
@@ -1453,18 +1452,18 @@ SIScheduleBlockScheduler::SIScheduleBlockScheduler(SIScheduleDAGMI *DAG,
14531452
}
14541453
#endif
14551454

1456-
std::set<unsigned> InRegs = DAG->getInRegs();
1455+
std::set<Register> InRegs = DAG->getInRegs();
14571456
addLiveRegs(InRegs);
14581457

14591458
// Increase LiveOutRegsNumUsages for blocks
14601459
// producing registers consumed in another
14611460
// scheduling region.
1462-
for (unsigned Reg : DAG->getOutRegs()) {
1461+
for (Register Reg : DAG->getOutRegs()) {
14631462
for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
14641463
// Do reverse traversal
14651464
int ID = BlocksStruct.TopDownIndex2Block[Blocks.size()-1-i];
14661465
SIScheduleBlock *Block = Blocks[ID];
1467-
const std::set<unsigned> &OutRegs = Block->getOutRegs();
1466+
const std::set<Register> &OutRegs = Block->getOutRegs();
14681467

14691468
if (OutRegs.find(Reg) == OutRegs.end())
14701469
continue;
@@ -1477,11 +1476,11 @@ SIScheduleBlockScheduler::SIScheduleBlockScheduler(SIScheduleDAGMI *DAG,
14771476
// Fill LiveRegsConsumers for regs that were already
14781477
// defined before scheduling.
14791478
for (SIScheduleBlock *Block : Blocks) {
1480-
for (unsigned Reg : Block->getInRegs()) {
1479+
for (Register Reg : Block->getInRegs()) {
14811480
bool Found = false;
14821481
for (SIScheduleBlock* Pred: Block->getPreds()) {
1483-
std::set<unsigned> PredOutRegs = Pred->getOutRegs();
1484-
std::set<unsigned>::iterator RegPos = PredOutRegs.find(Reg);
1482+
std::set<Register> PredOutRegs = Pred->getOutRegs();
1483+
std::set<Register>::iterator RegPos = PredOutRegs.find(Reg);
14851484

14861485
if (RegPos != PredOutRegs.end()) {
14871486
Found = true;
@@ -1573,13 +1572,11 @@ SIScheduleBlock *SIScheduleBlockScheduler::pickBlock() {
15731572
if (SregCurrentUsage > maxSregUsage)
15741573
maxSregUsage = SregCurrentUsage;
15751574
LLVM_DEBUG(dbgs() << "Picking New Blocks\n"; dbgs() << "Available: ";
1576-
for (SIScheduleBlock *Block
1577-
: ReadyBlocks) dbgs()
1578-
<< Block->getID() << ' ';
1575+
for (SIScheduleBlock *Block : ReadyBlocks)
1576+
dbgs() << Block->getID() << ' ';
15791577
dbgs() << "\nCurrent Live:\n";
1580-
for (unsigned Reg
1581-
: LiveRegs) dbgs()
1582-
<< printVRegOrUnit(Reg, DAG->getTRI()) << ' ';
1578+
for (Register Reg : LiveRegs)
1579+
dbgs() << printVRegOrUnit(Reg, DAG->getTRI()) << ' ';
15831580
dbgs() << '\n';
15841581
dbgs() << "Current VGPRs: " << VregCurrentUsage << '\n';
15851582
dbgs() << "Current SGPRs: " << SregCurrentUsage << '\n';);
@@ -1634,7 +1631,7 @@ SIScheduleBlock *SIScheduleBlockScheduler::pickBlock() {
16341631

16351632
// Tracking of currently alive registers to determine VGPR Usage.
16361633

1637-
void SIScheduleBlockScheduler::addLiveRegs(std::set<unsigned> &Regs) {
1634+
void SIScheduleBlockScheduler::addLiveRegs(std::set<Register> &Regs) {
16381635
for (Register Reg : Regs) {
16391636
// For now only track virtual registers.
16401637
if (!Reg.isVirtual())
@@ -1645,10 +1642,10 @@ void SIScheduleBlockScheduler::addLiveRegs(std::set<unsigned> &Regs) {
16451642
}
16461643

16471644
void SIScheduleBlockScheduler::decreaseLiveRegs(SIScheduleBlock *Block,
1648-
std::set<unsigned> &Regs) {
1649-
for (unsigned Reg : Regs) {
1645+
std::set<Register> &Regs) {
1646+
for (Register Reg : Regs) {
16501647
// For now only track virtual registers.
1651-
std::set<unsigned>::iterator Pos = LiveRegs.find(Reg);
1648+
std::set<Register>::iterator Pos = LiveRegs.find(Reg);
16521649
assert (Pos != LiveRegs.end() && // Reg must be live.
16531650
LiveRegsConsumers.find(Reg) != LiveRegsConsumers.end() &&
16541651
LiveRegsConsumers[Reg] >= 1);
@@ -1687,8 +1684,8 @@ void SIScheduleBlockScheduler::blockScheduled(SIScheduleBlock *Block) {
16871684
}
16881685

16891686
std::vector<int>
1690-
SIScheduleBlockScheduler::checkRegUsageImpact(std::set<unsigned> &InRegs,
1691-
std::set<unsigned> &OutRegs) {
1687+
SIScheduleBlockScheduler::checkRegUsageImpact(std::set<Register> &InRegs,
1688+
std::set<Register> &OutRegs) {
16921689
std::vector<int> DiffSetPressure;
16931690
DiffSetPressure.assign(DAG->getTRI()->getNumRegPressureSets(), 0);
16941691

‎llvm/lib/Target/AMDGPU/SIMachineScheduler.h‎

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -81,8 +81,8 @@ class SIScheduleBlock {
8181
// Note that some registers are not 32 bits,
8282
// and thus the pressure is not equal
8383
// to the number of live registers.
84-
std::set<unsigned> LiveInRegs;
85-
std::set<unsigned> LiveOutRegs;
84+
std::set<Register> LiveInRegs;
85+
std::set<Register> LiveOutRegs;
8686

8787
bool Scheduled = false;
8888
bool HighLatencyBlock = false;
@@ -157,8 +157,8 @@ class SIScheduleBlock {
157157
return InternalAdditionalPressure;
158158
}
159159

160-
std::set<unsigned> &getInRegs() { return LiveInRegs; }
161-
std::set<unsigned> &getOutRegs() { return LiveOutRegs; }
160+
std::set<Register> &getInRegs() { return LiveInRegs; }
161+
std::set<Register> &getOutRegs() { return LiveOutRegs; }
162162

163163
void printDebug(bool Full);
164164

@@ -320,10 +320,10 @@ class SIScheduleBlockScheduler {
320320
SISchedulerBlockSchedulerVariant Variant;
321321
std::vector<SIScheduleBlock*> Blocks;
322322

323-
std::vector<std::map<unsigned, unsigned>> LiveOutRegsNumUsages;
324-
std::set<unsigned> LiveRegs;
323+
std::vector<std::map<Register, unsigned>> LiveOutRegsNumUsages;
324+
std::set<Register> LiveRegs;
325325
// Num of schedulable unscheduled blocks reading the register.
326-
std::map<unsigned, unsigned> LiveRegsConsumers;
326+
std::map<Register, unsigned> LiveRegsConsumers;
327327

328328
std::vector<unsigned> LastPosHighLatencyParentScheduled;
329329
int LastPosWaitedHighLatency;
@@ -389,15 +389,15 @@ class SIScheduleBlockScheduler {
389389
SIBlockSchedCandidate &TryCand);
390390
SIScheduleBlock *pickBlock();
391391

392-
void addLiveRegs(std::set<unsigned> &Regs);
393-
void decreaseLiveRegs(SIScheduleBlock *Block, std::set<unsigned> &Regs);
392+
void addLiveRegs(std::set<Register> &Regs);
393+
void decreaseLiveRegs(SIScheduleBlock *Block, std::set<Register> &Regs);
394394
void releaseBlockSuccs(SIScheduleBlock *Parent);
395395
void blockScheduled(SIScheduleBlock *Block);
396396

397397
// Check register pressure change
398398
// by scheduling a block with these LiveIn and LiveOut.
399-
std::vector<int> checkRegUsageImpact(std::set<unsigned> &InRegs,
400-
std::set<unsigned> &OutRegs);
399+
std::vector<int> checkRegUsageImpact(std::set<Register> &InRegs,
400+
std::set<Register> &OutRegs);
401401

402402
void schedule();
403403
};
@@ -462,8 +462,8 @@ class SIScheduleDAGMI final : public ScheduleDAGMILive {
462462
unsigned &VgprUsage,
463463
unsigned &SgprUsage);
464464

465-
std::set<unsigned> getInRegs() {
466-
std::set<unsigned> InRegs;
465+
std::set<Register> getInRegs() {
466+
std::set<Register> InRegs;
467467
for (const auto &RegMaskPair : RPTracker.getPressure().LiveInRegs) {
468468
InRegs.insert(RegMaskPair.RegUnit);
469469
}

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