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RKSimonRKSimon
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[X86] printExtend - add support for mask predicated instructions
Remove handling from EmitAnyX86InstComments and handle all VPMOVSX/VPMOVZX comments in addConstantComments now that we can generically handle the destination + mask register and shuffle mask comment
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2 files changed

+26
-56
lines changed

2 files changed

+26
-56
lines changed

‎llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp‎

Lines changed: 0 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -65,16 +65,6 @@ using namespace llvm;
6565
CASE_AVX_INS_COMMON(Inst, Y, r##src) \
6666
CASE_SSE_INS_COMMON(Inst, r##src)
6767

68-
#define CASE_MASK_PMOVZX(Inst, src) \
69-
CASE_MASK_INS_COMMON(Inst, Z, r##src) \
70-
CASE_MASK_INS_COMMON(Inst, Z256, r##src) \
71-
CASE_MASK_INS_COMMON(Inst, Z128, r##src)
72-
73-
#define CASE_MASKZ_PMOVZX(Inst, src) \
74-
CASE_MASKZ_INS_COMMON(Inst, Z, r##src) \
75-
CASE_MASKZ_INS_COMMON(Inst, Z256, r##src) \
76-
CASE_MASKZ_INS_COMMON(Inst, Z128, r##src)
77-
7868
#define CASE_UNPCK(Inst, src) \
7969
CASE_AVX512_INS_COMMON(Inst, Z, r##src) \
8070
CASE_AVX512_INS_COMMON(Inst, Z256, r##src) \
@@ -1317,59 +1307,41 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
13171307

13181308
CASE_PMOVZX(PMOVZXBW, r)
13191309
Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1320-
[[fallthrough]];
1321-
CASE_MASK_PMOVZX(PMOVZXBW, m)
1322-
CASE_MASKZ_PMOVZX(PMOVZXBW, m)
13231310
DecodeZeroExtendMask(8, 16, getRegOperandNumElts(MI, 16, 0), false,
13241311
ShuffleMask);
13251312
DestName = getRegName(MI->getOperand(0).getReg());
13261313
break;
13271314

13281315
CASE_PMOVZX(PMOVZXBD, r)
13291316
Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1330-
[[fallthrough]];
1331-
CASE_MASK_PMOVZX(PMOVZXBD, m)
1332-
CASE_MASKZ_PMOVZX(PMOVZXBD, m)
13331317
DecodeZeroExtendMask(8, 32, getRegOperandNumElts(MI, 32, 0), false,
13341318
ShuffleMask);
13351319
DestName = getRegName(MI->getOperand(0).getReg());
13361320
break;
13371321

13381322
CASE_PMOVZX(PMOVZXBQ, r)
13391323
Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1340-
[[fallthrough]];
1341-
CASE_MASK_PMOVZX(PMOVZXBQ, m)
1342-
CASE_MASKZ_PMOVZX(PMOVZXBQ, m)
13431324
DecodeZeroExtendMask(8, 64, getRegOperandNumElts(MI, 64, 0), false,
13441325
ShuffleMask);
13451326
DestName = getRegName(MI->getOperand(0).getReg());
13461327
break;
13471328

13481329
CASE_PMOVZX(PMOVZXWD, r)
13491330
Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1350-
[[fallthrough]];
1351-
CASE_MASK_PMOVZX(PMOVZXWD, m)
1352-
CASE_MASKZ_PMOVZX(PMOVZXWD, m)
13531331
DecodeZeroExtendMask(16, 32, getRegOperandNumElts(MI, 32, 0), false,
13541332
ShuffleMask);
13551333
DestName = getRegName(MI->getOperand(0).getReg());
13561334
break;
13571335

13581336
CASE_PMOVZX(PMOVZXWQ, r)
13591337
Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1360-
[[fallthrough]];
1361-
CASE_MASK_PMOVZX(PMOVZXWQ, m)
1362-
CASE_MASKZ_PMOVZX(PMOVZXWQ, m)
13631338
DecodeZeroExtendMask(16, 64, getRegOperandNumElts(MI, 64, 0), false,
13641339
ShuffleMask);
13651340
DestName = getRegName(MI->getOperand(0).getReg());
13661341
break;
13671342

13681343
CASE_PMOVZX(PMOVZXDQ, r)
13691344
Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1370-
[[fallthrough]];
1371-
CASE_MASK_PMOVZX(PMOVZXDQ, m)
1372-
CASE_MASKZ_PMOVZX(PMOVZXDQ, m)
13731345
DecodeZeroExtendMask(32, 64, getRegOperandNumElts(MI, 64, 0), false,
13741346
ShuffleMask);
13751347
DestName = getRegName(MI->getOperand(0).getReg());

‎llvm/lib/Target/X86/X86MCInstLower.cpp‎

Lines changed: 26 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -1422,9 +1422,8 @@ static void printDstRegisterName(raw_ostream &CS, const MachineInstr *MI,
14221422
// MASKZ: zmmX {%kY} {z}
14231423
if (X86II::isKMasked(MI->getDesc().TSFlags)) {
14241424
const MachineOperand &WriteMaskOp = MI->getOperand(SrcOpIdx - 1);
1425-
CS << " {%";
1426-
CS << X86ATTInstPrinter::getRegisterName(WriteMaskOp.getReg());
1427-
CS << "}";
1425+
StringRef Mask = X86ATTInstPrinter::getRegisterName(WriteMaskOp.getReg());
1426+
CS << " {%" << Mask << "}";
14281427
if (!X86II::isKMergeMasked(MI->getDesc().TSFlags)) {
14291428
CS << " {z}";
14301429
}
@@ -1604,16 +1603,15 @@ static void printBroadcast(const MachineInstr *MI, MCStreamer &OutStreamer,
16041603

16051604
static bool printExtend(const MachineInstr *MI, MCStreamer &OutStreamer,
16061605
int SrcEltBits, int DstEltBits, bool IsSext) {
1607-
auto *C = X86::getConstantFromPool(*MI, 1);
1606+
unsigned SrcIdx = getSrcIdx(MI, 1);
1607+
auto *C = X86::getConstantFromPool(*MI, SrcIdx);
16081608
if (C && C->getType()->getScalarSizeInBits() == unsigned(SrcEltBits)) {
16091609
if (auto *CDS = dyn_cast<ConstantDataSequential>(C)) {
16101610
int NumElts = CDS->getNumElements();
16111611
std::string Comment;
16121612
raw_string_ostream CS(Comment);
1613-
1614-
const MachineOperand &DstOp = MI->getOperand(0);
1615-
CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = ";
1616-
CS << "[";
1613+
printDstRegisterName(CS, MI, SrcIdx);
1614+
CS << " = [";
16171615
for (int i = 0; i != NumElts; ++i) {
16181616
if (i != 0)
16191617
CS << ",";
@@ -1644,22 +1642,16 @@ static void printZeroExtend(const MachineInstr *MI, MCStreamer &OutStreamer,
16441642
// We didn't find a constant load, fallback to a shuffle mask decode.
16451643
std::string Comment;
16461644
raw_string_ostream CS(Comment);
1645+
printDstRegisterName(CS, MI, getSrcIdx(MI, 1));
1646+
CS << " = ";
16471647

1648-
const MachineOperand &DstOp = MI->getOperand(0);
1649-
CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = ";
1650-
1648+
SmallVector<int> Mask;
16511649
unsigned Width = getRegisterWidth(MI->getDesc().operands()[0]);
16521650
assert((Width % DstEltBits) == 0 && (DstEltBits % SrcEltBits) == 0 &&
16531651
"Illegal extension ratio");
1654-
unsigned NumElts = Width / DstEltBits;
1655-
unsigned Scale = DstEltBits / SrcEltBits;
1656-
for (unsigned I = 0; I != NumElts; ++I) {
1657-
if (I != 0)
1658-
CS << ",";
1659-
CS << "mem[" << I << "]";
1660-
for (unsigned S = 1; S != Scale; ++S)
1661-
CS << ",zero";
1662-
}
1652+
DecodeZeroExtendMask(SrcEltBits, DstEltBits, Width / DstEltBits, false, Mask);
1653+
printShuffleMask(CS, "mem", "", Mask);
1654+
16631655
OutStreamer.AddComment(CS.str());
16641656
}
16651657

@@ -2010,16 +2002,22 @@ static void addConstantComments(const MachineInstr *MI,
20102002
printBroadcast(MI, OutStreamer, 64, 8);
20112003
break;
20122004

2013-
#define MOVX_CASE(Prefix, Ext, Type, Suffix) \
2014-
case X86::Prefix##PMOV##Ext##Type##Suffix##rm:
2005+
#define MOVX_CASE(Prefix, Ext, Type, Suffix, Postfix) \
2006+
case X86::Prefix##PMOV##Ext##Type##Suffix##rm##Postfix:
20152007

20162008
#define CASE_MOVX_RM(Ext, Type) \
2017-
MOVX_CASE(, Ext, Type, ) \
2018-
MOVX_CASE(V, Ext, Type, ) \
2019-
MOVX_CASE(V, Ext, Type, Y) \
2020-
MOVX_CASE(V, Ext, Type, Z128) \
2021-
MOVX_CASE(V, Ext, Type, Z256) \
2022-
MOVX_CASE(V, Ext, Type, Z)
2009+
MOVX_CASE(, Ext, Type, , ) \
2010+
MOVX_CASE(V, Ext, Type, , ) \
2011+
MOVX_CASE(V, Ext, Type, Y, ) \
2012+
MOVX_CASE(V, Ext, Type, Z128, ) \
2013+
MOVX_CASE(V, Ext, Type, Z128, k ) \
2014+
MOVX_CASE(V, Ext, Type, Z128, kz ) \
2015+
MOVX_CASE(V, Ext, Type, Z256, ) \
2016+
MOVX_CASE(V, Ext, Type, Z256, k ) \
2017+
MOVX_CASE(V, Ext, Type, Z256, kz ) \
2018+
MOVX_CASE(V, Ext, Type, Z, ) \
2019+
MOVX_CASE(V, Ext, Type, Z, k ) \
2020+
MOVX_CASE(V, Ext, Type, Z, kz )
20232021

20242022
CASE_MOVX_RM(SX, BD)
20252023
printSignExtend(MI, OutStreamer, 8, 32);

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