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add ISEL pattern for fshr with uniform operands
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llvm/lib/Target/AMDGPU/SIInstructions.td

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@@ -2763,6 +2763,11 @@ def : GCNPat<(fshr i32:$src0, i32:$src1, i32:$src2),
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/* src2_modifiers */ 0,
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$src2, /* clamp */ 0, /* op_sel */ 0)
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>;
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def : GCNPat<(UniformTernaryFrag<fshr> i32:$src0, i32:$src1, i32:$src2),
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(S_OR_B32 (S_LSHR_B32 $src1, (S_AND_B32 $src2, (i32 0xffffffff))), (S_LSHL_B32 $src0, (S_SUB_I32 (i32 32), (S_AND_B32 $src2, (i32 0xffffffff)))))
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>;
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} // end True16Predicate = UseFakeTrue16Insts
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/********** ====================== **********/

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