fix tests

Author: el-ev

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

@@ -2991,14 +2991,20 @@ bool TargetLowering::SimplifyDemandedBits(
   case ISD::FCOPYSIGN: {
     SDValue Op0 = Op.getOperand(0);
     SDValue Op1 = Op.getOperand(1);
-    APInt SignMask = APInt::getSignMask(BitWidth);
 
-    if (!DemandedBits.intersects(SignMask))
+    unsigned BitWidth0 = Op0.getScalarValueSizeInBits();
+    unsigned BitWidth1 = Op1.getScalarValueSizeInBits();
+    APInt SignMask0 = APInt::getSignMask(BitWidth0);
+    APInt SignMask1 = APInt::getSignMask(BitWidth1);
+
+    if (!DemandedBits.intersects(SignMask0))
       return TLO.CombineTo(Op, Op0);
 
-    if (SimplifyDemandedBits(Op0, ~SignMask & DemandedBits, DemandedElts, Known,
-                             TLO, Depth + 1) ||
-        SimplifyDemandedBits(Op1, SignMask, DemandedElts, Known2, TLO,
+    APInt ScalarDemandedBits = DemandedBits.trunc(BitWidth0);
+
+    if (SimplifyDemandedBits(Op0, ~SignMask0 & ScalarDemandedBits, DemandedElts,
+                             Known, TLO, Depth + 1) ||
+        SimplifyDemandedBits(Op1, SignMask1, DemandedElts, Known2, TLO,
                              Depth + 1))
       return true;
 
@@ -3011,8 +3017,8 @@ bool TargetLowering::SimplifyDemandedBits(
           Op, TLO.DAG.getNode(ISD::FABS, dl, VT, Op0, Op->getFlags()));
 
     if (Known2.isNegative()) {
-      Known.One |= SignMask;
-      Known.Zero &= ~SignMask;
+      Known.One |= SignMask0;
+      Known.Zero &= ~SignMask0;
     }
 
     break;

llvm/test/CodeGen/AMDGPU/fabs.bf16.ll

@@ -220,7 +220,7 @@ define amdgpu_kernel void @s_fabs_v4bf16(ptr addrspace(1) %out, <4 x bfloat> %in
 ; CI-NEXT:    s_waitcnt lgkmcnt(0)
 ; CI-NEXT:    s_and_b32 s4, s3, 0xffff0000
 ; CI-NEXT:    s_lshl_b32 s3, s3, 16
-; CI-NEXT:    s_and_b32 s5, s2, 0xffff0000
+; CI-NEXT:    s_and_b32 s5, s2, 0x7fff0000
 ; CI-NEXT:    v_mul_f32_e64 v0, 1.0, |s4|
 ; CI-NEXT:    v_mul_f32_e64 v1, 1.0, |s3|
 ; CI-NEXT:    v_mul_f32_e64 v2, 1.0, |s5|
@@ -944,7 +944,7 @@ define amdgpu_kernel void @v_extract_fabs_fold_v2bf16(ptr addrspace(1) %in) #0 {
 ; CI-NEXT:    flat_load_dword v0, v[0:1]
 ; CI-NEXT:    s_waitcnt vmcnt(0)
 ; CI-NEXT:    v_lshlrev_b32_e32 v1, 16, v0
-; CI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; CI-NEXT:    v_and_b32_e32 v0, 0x7fff0000, v0
 ; CI-NEXT:    v_mul_f32_e64 v1, 1.0, |v1|
 ; CI-NEXT:    v_mul_f32_e64 v0, 1.0, |v0|
 ; CI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1

llvm/test/CodeGen/AMDGPU/fneg-fabs.bf16.ll

@@ -481,17 +481,16 @@ define amdgpu_kernel void @s_fneg_fabs_v2bf16_non_bc_src(ptr addrspace(1) %out,
 ; CI-NEXT:    s_lshl_b32 s2, s2, 16
 ; CI-NEXT:    v_add_f32_e64 v0, s3, 2.0
 ; CI-NEXT:    v_add_f32_e64 v1, s2, 1.0
-; CI-NEXT:    v_readfirstlane_b32 s2, v0
-; CI-NEXT:    s_and_b32 s2, s2, 0xffff0000
-; CI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
-; CI-NEXT:    s_bitset0_b32 s2, 31
-; CI-NEXT:    v_and_b32_e32 v0, 0x7fffffff, v1
-; CI-NEXT:    s_and_b32 s2, s2, 0xffff0000
-; CI-NEXT:    s_xor_b32 s2, s2, 0x80000000
+; CI-NEXT:    v_and_b32_e32 v0, 0x7fff0000, v0
+; CI-NEXT:    v_and_b32_e32 v1, 0x7fff0000, v1
+; CI-NEXT:    v_mul_f32_e64 v0, 1.0, |v0|
+; CI-NEXT:    v_mul_f32_e64 v1, 1.0, |v1|
 ; CI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
-; CI-NEXT:    s_lshr_b32 s2, s2, 16
 ; CI-NEXT:    v_xor_b32_e32 v0, 0x80000000, v0
-; CI-NEXT:    v_alignbit_b32 v2, s2, v0, 16
+; CI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
+; CI-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; CI-NEXT:    v_xor_b32_e32 v1, 0x80000000, v1
+; CI-NEXT:    v_alignbit_b32 v2, v0, v1, 16
 ; CI-NEXT:    v_mov_b32_e32 v0, s0
 ; CI-NEXT:    v_mov_b32_e32 v1, s1
 ; CI-NEXT:    flat_store_dword v[0:1], v2
@@ -676,7 +675,7 @@ define amdgpu_kernel void @fneg_fabs_v4bf16(ptr addrspace(1) %out, <4 x bfloat>
 ; CI-NEXT:    s_lshr_b32 flat_scratch_hi, s12, 8
 ; CI-NEXT:    s_waitcnt lgkmcnt(0)
 ; CI-NEXT:    s_lshl_b32 s4, s2, 16
-; CI-NEXT:    s_and_b32 s2, s2, 0xffff0000
+; CI-NEXT:    s_and_b32 s2, s2, 0x7fff0000
 ; CI-NEXT:    v_mul_f32_e64 v2, 1.0, |s2|
 ; CI-NEXT:    s_and_b32 s2, s3, 0xffff0000
 ; CI-NEXT:    s_lshl_b32 s5, s3, 16