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fhahnfhahn
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!fixup adjust types and naming, thanks
1 parent eac3396 commit f4c82b9

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2 files changed

+19
-31
lines changed

2 files changed

+19
-31
lines changed

‎llvm/lib/Transforms/Vectorize/VectorCombine.cpp‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1829,15 +1829,15 @@ bool VectorCombine::scalarizeExtExtract(Instruction &I) {
18291829
ScalarV = Builder.CreateBitCast(
18301830
ScalarV,
18311831
IntegerType::get(SrcTy->getContext(), DL->getTypeSizeInBits(SrcTy)));
1832-
unsigned SrcEltSizeInBits = DL->getTypeSizeInBits(SrcTy->getElementType());
1833-
unsigned EltBitMask = (1ull << SrcEltSizeInBits) - 1;
1832+
uint64_t SrcEltSizeInBits = DL->getTypeSizeInBits(SrcTy->getElementType());
1833+
uint64_t EltBitMask = (1ull << SrcEltSizeInBits) - 1;
18341834
for (User *U : Ext->users()) {
18351835
auto *Extract = cast<ExtractElementInst>(U);
18361836
uint64_t Idx =
18371837
cast<ConstantInt>(Extract->getIndexOperand())->getZExtValue();
1838-
Value *S = Builder.CreateLShr(ScalarV, Idx * SrcEltSizeInBits);
1839-
Value *A = Builder.CreateAnd(S, EltBitMask);
1840-
U->replaceAllUsesWith(A);
1838+
Value *LShr = Builder.CreateLShr(ScalarV, Idx * SrcEltSizeInBits);
1839+
Value *And = Builder.CreateAnd(LShr, EltBitMask);
1840+
U->replaceAllUsesWith(And);
18411841
}
18421842
return true;
18431843
}

‎llvm/test/Transforms/VectorCombine/AArch64/ext-extract.ll‎

Lines changed: 14 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -12,13 +12,11 @@ define void @zext_v4i8_all_lanes_used(<4 x i8> %src) {
1212
; CHECK-NEXT: [[TMP0:%.*]] = freeze <4 x i8> [[SRC]]
1313
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[TMP0]] to i32
1414
; CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP1]], 24
15-
; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP2]], 255
1615
; CHECK-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP1]], 16
1716
; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP4]], 255
1817
; CHECK-NEXT: [[TMP6:%.*]] = lshr i32 [[TMP1]], 8
1918
; CHECK-NEXT: [[TMP7:%.*]] = and i32 [[TMP6]], 255
20-
; CHECK-NEXT: [[TMP8:%.*]] = lshr i32 [[TMP1]], 0
21-
; CHECK-NEXT: [[TMP9:%.*]] = and i32 [[TMP8]], 255
19+
; CHECK-NEXT: [[TMP9:%.*]] = and i32 [[TMP1]], 255
2220
; CHECK-NEXT: [[EXT9:%.*]] = zext nneg <4 x i8> [[SRC]] to <4 x i32>
2321
; CHECK-NEXT: [[EXT_0:%.*]] = extractelement <4 x i32> [[EXT9]], i64 0
2422
; CHECK-NEXT: [[EXT_1:%.*]] = extractelement <4 x i32> [[EXT9]], i64 1
@@ -27,7 +25,7 @@ define void @zext_v4i8_all_lanes_used(<4 x i8> %src) {
2725
; CHECK-NEXT: call void @use.i32(i32 [[TMP9]])
2826
; CHECK-NEXT: call void @use.i32(i32 [[TMP7]])
2927
; CHECK-NEXT: call void @use.i32(i32 [[TMP5]])
30-
; CHECK-NEXT: call void @use.i32(i32 [[TMP3]])
28+
; CHECK-NEXT: call void @use.i32(i32 [[TMP2]])
3129
; CHECK-NEXT: ret void
3230
;
3331
entry:
@@ -81,7 +79,6 @@ define void @zext_v4i8_3_lanes_used_1(<4 x i8> %src) {
8179
; CHECK-NEXT: [[TMP0:%.*]] = freeze <4 x i8> [[SRC]]
8280
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[TMP0]] to i32
8381
; CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP1]], 24
84-
; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP2]], 255
8582
; CHECK-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP1]], 16
8683
; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP4]], 255
8784
; CHECK-NEXT: [[TMP6:%.*]] = lshr i32 [[TMP1]], 8
@@ -92,7 +89,7 @@ define void @zext_v4i8_3_lanes_used_1(<4 x i8> %src) {
9289
; CHECK-NEXT: [[EXT_3:%.*]] = extractelement <4 x i32> [[EXT9]], i64 3
9390
; CHECK-NEXT: call void @use.i32(i32 [[TMP7]])
9491
; CHECK-NEXT: call void @use.i32(i32 [[TMP5]])
95-
; CHECK-NEXT: call void @use.i32(i32 [[TMP3]])
92+
; CHECK-NEXT: call void @use.i32(i32 [[TMP2]])
9693
; CHECK-NEXT: ret void
9794
;
9895
entry:
@@ -114,18 +111,16 @@ define void @zext_v4i8_3_lanes_used_2(<4 x i8> %src) {
114111
; CHECK-NEXT: [[TMP0:%.*]] = freeze <4 x i8> [[SRC]]
115112
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[TMP0]] to i32
116113
; CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP1]], 24
117-
; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP2]], 255
118114
; CHECK-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP1]], 8
119115
; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP4]], 255
120-
; CHECK-NEXT: [[TMP6:%.*]] = lshr i32 [[TMP1]], 0
121-
; CHECK-NEXT: [[TMP7:%.*]] = and i32 [[TMP6]], 255
116+
; CHECK-NEXT: [[TMP7:%.*]] = and i32 [[TMP1]], 255
122117
; CHECK-NEXT: [[EXT9:%.*]] = zext nneg <4 x i8> [[SRC]] to <4 x i32>
123118
; CHECK-NEXT: [[EXT_0:%.*]] = extractelement <4 x i32> [[EXT9]], i64 0
124119
; CHECK-NEXT: [[EXT_1:%.*]] = extractelement <4 x i32> [[EXT9]], i64 1
125120
; CHECK-NEXT: [[EXT_3:%.*]] = extractelement <4 x i32> [[EXT9]], i64 3
126121
; CHECK-NEXT: call void @use.i32(i32 [[TMP7]])
127122
; CHECK-NEXT: call void @use.i32(i32 [[TMP5]])
128-
; CHECK-NEXT: call void @use.i32(i32 [[TMP3]])
123+
; CHECK-NEXT: call void @use.i32(i32 [[TMP2]])
129124
; CHECK-NEXT: ret void
130125
;
131126
entry:
@@ -175,8 +170,7 @@ define void @zext_v4i8_2_lanes_used_2(<4 x i8> %src) {
175170
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[TMP0]] to i32
176171
; CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP1]], 16
177172
; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP2]], 255
178-
; CHECK-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP1]], 0
179-
; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP4]], 255
173+
; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP1]], 255
180174
; CHECK-NEXT: [[EXT9:%.*]] = zext nneg <4 x i8> [[SRC]] to <4 x i32>
181175
; CHECK-NEXT: [[EXT_0:%.*]] = extractelement <4 x i32> [[EXT9]], i64 0
182176
; CHECK-NEXT: [[EXT_2:%.*]] = extractelement <4 x i32> [[EXT9]], i64 2
@@ -200,13 +194,11 @@ define void @zext_v4i8_all_lanes_used_noundef(<4 x i8> noundef %src) {
200194
; CHECK-NEXT: [[ENTRY:.*:]]
201195
; CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i8> [[SRC]] to i32
202196
; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[TMP0]], 24
203-
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 255
204197
; CHECK-NEXT: [[TMP3:%.*]] = lshr i32 [[TMP0]], 16
205198
; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[TMP3]], 255
206199
; CHECK-NEXT: [[TMP5:%.*]] = lshr i32 [[TMP0]], 8
207200
; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[TMP5]], 255
208-
; CHECK-NEXT: [[TMP7:%.*]] = lshr i32 [[TMP0]], 0
209-
; CHECK-NEXT: [[TMP8:%.*]] = and i32 [[TMP7]], 255
201+
; CHECK-NEXT: [[TMP8:%.*]] = and i32 [[TMP0]], 255
210202
; CHECK-NEXT: [[EXT9:%.*]] = zext nneg <4 x i8> [[SRC]] to <4 x i32>
211203
; CHECK-NEXT: [[EXT_0:%.*]] = extractelement <4 x i32> [[EXT9]], i64 0
212204
; CHECK-NEXT: [[EXT_1:%.*]] = extractelement <4 x i32> [[EXT9]], i64 1
@@ -215,7 +207,7 @@ define void @zext_v4i8_all_lanes_used_noundef(<4 x i8> noundef %src) {
215207
; CHECK-NEXT: call void @use.i32(i32 [[TMP8]])
216208
; CHECK-NEXT: call void @use.i32(i32 [[TMP6]])
217209
; CHECK-NEXT: call void @use.i32(i32 [[TMP4]])
218-
; CHECK-NEXT: call void @use.i32(i32 [[TMP2]])
210+
; CHECK-NEXT: call void @use.i32(i32 [[TMP1]])
219211
; CHECK-NEXT: ret void
220212
;
221213
entry:
@@ -271,13 +263,11 @@ define void @zext_v4i16_all_lanes_used(<4 x i16> %src) {
271263
; CHECK-NEXT: [[TMP0:%.*]] = freeze <4 x i16> [[SRC]]
272264
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[TMP0]] to i64
273265
; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 48
274-
; CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], 65535
275266
; CHECK-NEXT: [[TMP4:%.*]] = lshr i64 [[TMP1]], 32
276267
; CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 65535
277268
; CHECK-NEXT: [[TMP6:%.*]] = lshr i64 [[TMP1]], 16
278269
; CHECK-NEXT: [[TMP7:%.*]] = and i64 [[TMP6]], 65535
279-
; CHECK-NEXT: [[TMP8:%.*]] = lshr i64 [[TMP1]], 0
280-
; CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 65535
270+
; CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP1]], 65535
281271
; CHECK-NEXT: [[EXT9:%.*]] = zext nneg <4 x i16> [[SRC]] to <4 x i64>
282272
; CHECK-NEXT: [[EXT_0:%.*]] = extractelement <4 x i64> [[EXT9]], i64 0
283273
; CHECK-NEXT: [[EXT_1:%.*]] = extractelement <4 x i64> [[EXT9]], i64 1
@@ -286,7 +276,7 @@ define void @zext_v4i16_all_lanes_used(<4 x i16> %src) {
286276
; CHECK-NEXT: call void @use.i64(i64 [[TMP9]])
287277
; CHECK-NEXT: call void @use.i64(i64 [[TMP7]])
288278
; CHECK-NEXT: call void @use.i64(i64 [[TMP5]])
289-
; CHECK-NEXT: call void @use.i64(i64 [[TMP3]])
279+
; CHECK-NEXT: call void @use.i64(i64 [[TMP2]])
290280
; CHECK-NEXT: ret void
291281
;
292282
entry:
@@ -310,14 +300,12 @@ define void @zext_v2i32_all_lanes_used(<2 x i32> %src) {
310300
; CHECK-NEXT: [[TMP0:%.*]] = freeze <2 x i32> [[SRC]]
311301
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to i64
312302
; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 32
313-
; CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], 4294967295
314-
; CHECK-NEXT: [[TMP4:%.*]] = lshr i64 [[TMP1]], 0
315-
; CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 4294967295
303+
; CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP1]], 4294967295
316304
; CHECK-NEXT: [[EXT9:%.*]] = zext nneg <2 x i32> [[SRC]] to <2 x i64>
317305
; CHECK-NEXT: [[EXT_0:%.*]] = extractelement <2 x i64> [[EXT9]], i64 0
318306
; CHECK-NEXT: [[EXT_1:%.*]] = extractelement <2 x i64> [[EXT9]], i64 1
319307
; CHECK-NEXT: call void @use.i64(i64 [[TMP5]])
320-
; CHECK-NEXT: call void @use.i64(i64 [[TMP3]])
308+
; CHECK-NEXT: call void @use.i64(i64 [[TMP2]])
321309
; CHECK-NEXT: ret void
322310
;
323311
entry:
@@ -330,8 +318,8 @@ entry:
330318
ret void
331319
}
332320

333-
define void @zext_nv4i8_all_lanes_used(<vscale x 4 x i8> %src) {
334-
; CHECK-LABEL: define void @zext_nv4i8_all_lanes_used(
321+
define void @zext_nxv4i8_all_lanes_used(<vscale x 4 x i8> %src) {
322+
; CHECK-LABEL: define void @zext_nxv4i8_all_lanes_used(
335323
; CHECK-SAME: <vscale x 4 x i8> [[SRC:%.*]]) {
336324
; CHECK-NEXT: [[ENTRY:.*:]]
337325
; CHECK-NEXT: [[EXT9:%.*]] = zext nneg <vscale x 4 x i8> [[SRC]] to <vscale x 4 x i32>

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