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[AMDGPU] Scavenge a VGPR to eliminate FI
If the subtarget supports flat scratch SVS mode and there is no SGPR available to replace a frame index, convert a scratch instruction in SS form into SV form by scavenging a VGPR. Co-authored by Matt Arsenault
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2 files changed

+498
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llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

Lines changed: 29 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2983,10 +2983,36 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
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: RS->scavengeRegisterBackwards(AMDGPU::SReg_32_XM0RegClass,
29842984
MI, false, 0, !UseSGPR);
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2986-
// TODO: for flat scratch another attempt can be made with a VGPR index
2987-
// if no SGPRs can be scavenged.
2988-
if ((!TmpSReg && !FrameReg) || (!TmpReg && !UseSGPR))
2986+
if ((!TmpSReg && !FrameReg) || (!TmpReg && !UseSGPR)) {
2987+
if (ST.hasFlatScratchSVSMode()) {
2988+
int SVOpcode = AMDGPU::getFlatScratchInstSVfromSS(MI->getOpcode());
2989+
Register TmpVGPR = RS->scavengeRegisterBackwards(
2990+
AMDGPU::VGPR_32RegClass, MI, false, 0, /*AllowSpill=*/true);
2991+
2992+
// Materialize the frame register.
2993+
auto MIB =
2994+
BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), TmpVGPR);
2995+
if (FrameReg)
2996+
MIB.addReg(FrameReg);
2997+
else
2998+
MIB.addImm(Offset);
2999+
3000+
// Add the offset to the frame register.
3001+
if (FrameReg && Offset)
3002+
BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_ADD_U32_e32), FrameReg)
3003+
.addReg(FrameReg, RegState::Kill)
3004+
.addImm(Offset);
3005+
3006+
BuildMI(*MBB, MI, DL, TII->get(SVOpcode))
3007+
.add(MI->getOperand(0)) // $vdata
3008+
.addReg(TmpVGPR) // $vaddr
3009+
.addImm(0) // Offset
3010+
.add(*TII->getNamedOperand(*MI, AMDGPU::OpName::cpol));
3011+
MI->eraseFromParent();
3012+
return true;
3013+
}
29893014
report_fatal_error("Cannot scavenge register in FI elimination!");
3015+
}
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29913017
if (!TmpSReg) {
29923018
// Use frame register and restore it after.

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