Update llvm/test/CodeGen/AMDGPU/load-store-opt-ds-regclass-constrain.mir

Co-authored-by: Matt Arsenault <[email protected]>

Author: niconunezz

llvm/test/CodeGen/AMDGPU/load-store-opt-ds-regclass-constrain.mir

@@ -286,4 +286,6 @@ body:             |
   %0:vgpr_32 = COPY $vgpr0
   %2:av_64_align2 = COPY $vgpr4_vgpr5
   DS_WRITE_B64_gfx9 %0, $vgpr2_vgpr3, 40, 0, implicit $exec :: (store (s64), addrspace 3)
-  DS_WRITE_B64_gfx9 %0, %2, 96, 0, implicit $exec :: (store (s64), addrspace 3)
+  DS_WRITE_B64_gfx9 %0, %2, 96, 0, implicit $exec :: (store (s64), addrspace 3)
+  ...
+