fixup! Use WidenV for vfwmacc.4x4x4 and vqmacc*.4x8x4.

topperc · topperc · commit f55f90c2f186 · 2025-01-22T19:57:03.000-08:00
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
@@ -210,15 +210,15 @@ let Predicates = [HasVendorXSfvqmaccdod], DecoderNamespace = "XSfvqmaccdod",
 }
 
 let Predicates = [HasVendorXSfvqmaccqoq], DecoderNamespace = "XSfvqmaccqoq",
-    DestEEW = EEWSEWx4, RVVConstraint=VS2Constraint in {
+    DestEEW = EEWSEWx4, RVVConstraint=WidenV in {
   def VQMACCU_4x8x4  : CustomSiFiveVMACC<0b111100, OPMVV, "sf.vqmaccu.4x8x4">;
   def VQMACC_4x8x4   : CustomSiFiveVMACC<0b111101, OPMVV, "sf.vqmacc.4x8x4">;
   def VQMACCUS_4x8x4 : CustomSiFiveVMACC<0b111110, OPMVV, "sf.vqmaccus.4x8x4">;
   def VQMACCSU_4x8x4 : CustomSiFiveVMACC<0b111111, OPMVV, "sf.vqmaccsu.4x8x4">;
 }
 
 let Predicates = [HasVendorXSfvfwmaccqqq], DecoderNamespace = "XSfvfwmaccqqq",
-    DestEEW = EEWSEWx2, RVVConstraint=VS2Constraint in {
+    DestEEW = EEWSEWx2, RVVConstraint=WidenV in {
   def VFWMACC_4x4x4 : CustomSiFiveVMACC<0b111100, OPFVV, "sf.vfwmacc.4x4x4">;
 }
 
diff --git a/llvm/test/MC/RISCV/rvv/xsfvfwmacc-invalid.s b/llvm/test/MC/RISCV/rvv/xsfvfwmacc-invalid.s
@@ -4,3 +4,7 @@
 sf.vfwmacc.4x4x4 v8, v8, v20
 # CHECK-ERROR: the destination vector register group cannot overlap the source vector register group{{$}}
 # CHECK-ERROR-LABEL: sf.vfwmacc.4x4x4 v8, v8, v20{{$}}
+
+sf.vfwmacc.4x4x4 v8, v4, v8
+# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group{{$}}
+# CHECK-ERROR-LABEL: sf.vfwmacc.4x4x4 v8, v4, v8{{$}}
diff --git a/llvm/test/MC/RISCV/rvv/xsfvqmacc-invalid.s b/llvm/test/MC/RISCV/rvv/xsfvqmacc-invalid.s
@@ -32,3 +32,19 @@ sf.vqmaccus.4x8x4 v8, v8, v20
 sf.vqmaccsu.4x8x4 v8, v8, v20
 # CHECK-ERROR: the destination vector register group cannot overlap the source vector register group{{$}}
 # CHECK-ERROR-LABEL: sf.vqmaccsu.4x8x4 v8, v8, v20
+
+sf.vqmaccu.4x8x4 v8, v4, v8
+# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group{{$}}
+# CHECK-ERROR-LABEL: sf.vqmaccu.4x8x4 v8, v4, v8
+
+sf.vqmacc.4x8x4 v8, v4, v8
+# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group{{$}}
+# CHECK-ERROR-LABEL: sf.vqmacc.4x8x4 v8, v4, v8
+
+sf.vqmaccus.4x8x4 v8, v4, v8
+# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group{{$}}
+# CHECK-ERROR-LABEL: sf.vqmaccus.4x8x4 v8, v4, v8
+
+sf.vqmaccsu.4x8x4 v8, v4, v8
+# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group{{$}}
+# CHECK-ERROR-LABEL: sf.vqmaccsu.4x8x4 v8, v4, v8

Original file line number	Diff line number	Diff line change
`@@ -210,15 +210,15 @@ let Predicates = [HasVendorXSfvqmaccdod], DecoderNamespace = "XSfvqmaccdod",`
`210`	`210`	`}`
`211`	`211`
`212`	`212`	`let Predicates = [HasVendorXSfvqmaccqoq], DecoderNamespace = "XSfvqmaccqoq",`
`213`		`- DestEEW = EEWSEWx4, RVVConstraint=VS2Constraint in {`
	`213`	`+ DestEEW = EEWSEWx4, RVVConstraint=WidenV in {`
`214`	`214`	`def VQMACCU_4x8x4 : CustomSiFiveVMACC<0b111100, OPMVV, "sf.vqmaccu.4x8x4">;`
`215`	`215`	`def VQMACC_4x8x4 : CustomSiFiveVMACC<0b111101, OPMVV, "sf.vqmacc.4x8x4">;`
`216`	`216`	`def VQMACCUS_4x8x4 : CustomSiFiveVMACC<0b111110, OPMVV, "sf.vqmaccus.4x8x4">;`
`217`	`217`	`def VQMACCSU_4x8x4 : CustomSiFiveVMACC<0b111111, OPMVV, "sf.vqmaccsu.4x8x4">;`
`218`	`218`	`}`
`219`	`219`
`220`	`220`	`let Predicates = [HasVendorXSfvfwmaccqqq], DecoderNamespace = "XSfvfwmaccqqq",`
`221`		`- DestEEW = EEWSEWx2, RVVConstraint=VS2Constraint in {`
	`221`	`+ DestEEW = EEWSEWx2, RVVConstraint=WidenV in {`
`222`	`222`	`def VFWMACC_4x4x4 : CustomSiFiveVMACC<0b111100, OPFVV, "sf.vfwmacc.4x4x4">;`
`223`	`223`	`}`
`224`	`224`