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fixup! [AArch64][llvm] Add support for Permission Overlays Extension 2 (FEAT_S1POE2)
Fix CR issues
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5 files changed

+29
-82
lines changed

5 files changed

+29
-82
lines changed

‎llvm/lib/Target/AArch64/AArch64InstrFormats.td‎

Lines changed: 4 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -13422,8 +13422,7 @@ class TENTERInst<string asm> : I<
1342213422
asm, "\t$imm, $nb", "", []>, Sched<[]> {
1342313423
bits<7> imm;
1342413424
bits<1> nb;
13425-
let Inst{31-20} = 0b110101001110;
13426-
let Inst{19-18} = 0b00;
13425+
let Inst{31-18} = 0b11010100111000;
1342713426
let Inst{17} = nb;
1342813427
let Inst{16-12} = 0b00000;
1342913428
let Inst{11-5} = imm;
@@ -13435,8 +13434,7 @@ class TEXITInst<string asm> : I<
1343513434
(ins TIndexhint_op:$nb),
1343613435
asm, "\t$nb", "", []>, Sched<[]> {
1343713436
bits<1> nb;
13438-
let Inst{31-13} = 0b1101011011111111000;
13439-
let Inst{12-11} = 0b00;
13437+
let Inst{31-11} = 0b110101101111111100000;
1344013438
let Inst{10} = nb;
1344113439
let Inst{9-0} = 0b1111100000;
1344213440
}
@@ -13450,8 +13448,8 @@ multiclass TCHANGEReg<string asm , bit isB> {
1345013448

1345113449
multiclass TCHANGEImm<string asm, bit isB> {
1345213450
def NAME : TCHANGEImmInst<asm, isB>;
13453-
def : InstAlias<asm # "\t$Xd, $Xn",
13454-
(!cast<Instruction>(NAME) GPR64:$Xd, imm0_127:$Xn, 0), 1>;
13451+
def : InstAlias<asm # "\t$Xd, $imm",
13452+
(!cast<Instruction>(NAME) GPR64:$Xd, imm0_127:$imm, 0), 1>;
1345513453
}
1345613454

1345713455
multiclass TENTER<string asm> {

‎llvm/lib/Target/AArch64/AArch64SystemOperands.td‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -819,7 +819,6 @@ def : BTI<"c", 0b010>;
819819
def : BTI<"j", 0b100>;
820820
def : BTI<"jc", 0b110>;
821821

822-
823822
//===----------------------------------------------------------------------===//
824823
// CMHPriority instruction options.
825824
//===----------------------------------------------------------------------===//
@@ -2862,7 +2861,7 @@ multiclass PLBI<string name, bits<3> op1, bits<4> crn, bits<3> op2,
28622861

28632862
// CRm defines above six variants of each instruction. It is omitted here.
28642863
// Op1 CRn Op2 needsreg
2865-
defm : PLBI<"ALLE3", 0b110, 0b1010, 0b000, 0>;
2864+
defm : PLBI<"ALLE3", 0b110, 0b1010, 0b000, 1>;
28662865
defm : PLBI<"ALLE2", 0b100, 0b1010, 0b000, 0>;
28672866
defm : PLBI<"ALLE1", 0b100, 0b1010, 0b100, 0>;
28682867
defm : PLBI<"VMALLE1", 0b000, 0b1010, 0b000, 0>;

‎llvm/test/MC/AArch64/arm-poe2-tlbid-diagnostics.s‎

Lines changed: 0 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -5,12 +5,6 @@
55

66
// Test without using +tlbid - no optional register operand allowed
77

8-
plbi alle3is, x0
9-
// CHECK-ERROR: error: specified plbi op does not use a register
10-
11-
plbi alle3os, x0
12-
// CHECK-ERROR: error: specified plbi op does not use a register
13-
148
plbi alle2is, x0
159
// CHECK-ERROR: error: specified plbi op does not use a register
1610

@@ -29,12 +23,6 @@ plbi vmalle1is, x0
2923
plbi vmalle1os, x0
3024
// CHECK-ERROR: error: specified plbi op does not use a register
3125

32-
plbi alle3isnxs, x0
33-
// CHECK-ERROR: error: specified plbi op does not use a register
34-
35-
plbi alle3osnxs, x0
36-
// CHECK-ERROR: error: specified plbi op does not use a register
37-
3826
plbi alle2isnxs, x0
3927
// CHECK-ERROR: error: specified plbi op does not use a register
4028

@@ -54,10 +42,6 @@ plbi vmalle1osnxs, x0
5442
// CHECK-ERROR: error: specified plbi op does not use a register
5543

5644
// Tests where no optional register operand allowed
57-
plbi alle3, x0
58-
// CHECK-ERROR: error: specified plbi op does not use a register
59-
// CHECK-NO-REGISTER: error: specified plbi op does not use a register
60-
6145
plbi alle2, x0
6246
// CHECK-ERROR: error: specified plbi op does not use a register
6347
// CHECK-NO-REGISTER: error: specified plbi op does not use a register
@@ -70,10 +54,6 @@ plbi vmalle1, x0
7054
// CHECK-ERROR: error: specified plbi op does not use a register
7155
// CHECK-NO-REGISTER: error: specified plbi op does not use a register
7256

73-
plbi alle3nxs, x0
74-
// CHECK-ERROR: error: specified plbi op does not use a register
75-
// CHECK-NO-REGISTER: error: specified plbi op does not use a register
76-
7757
plbi alle2nxs, x0
7858
// CHECK-ERROR: error: specified plbi op does not use a register
7959
// CHECK-NO-REGISTER: error: specified plbi op does not use a register

‎llvm/test/MC/AArch64/arm-poe2-tlbid.s‎

Lines changed: 0 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -14,18 +14,6 @@
1414

1515
// FEAT_TLBID and POE2 combined
1616

17-
plbi alle3is, x0
18-
// CHECK-INST: plbi alle3is, x0
19-
// CHECK-ENCODING: encoding: [0x00,0xa3,0x0e,0xd5]
20-
// CHECK-ERROR: error: specified plbi op does not use a register
21-
// CHECK-UNKNOWN: d50ea300 sys #6, c10, c3, #0, x0
22-
23-
plbi alle3os, x0
24-
// CHECK-INST: plbi alle3os, x0
25-
// CHECK-ENCODING: encoding: [0x00,0xa1,0x0e,0xd5]
26-
// CHECK-ERROR: error: specified plbi op does not use a register
27-
// CHECK-UNKNOWN: d50ea100 sys #6, c10, c1, #0, x0
28-
2917
plbi alle2is, x0
3018
// CHECK-INST: plbi alle2is, x0
3119
// CHECK-ENCODING: encoding: [0x00,0xa3,0x0c,0xd5]
@@ -62,18 +50,6 @@ plbi vmalle1os, x0
6250
// CHECK-ERROR: error: specified plbi op does not use a register
6351
// CHECK-UNKNOWN: d508a100 sys #0, c10, c1, #0, x0
6452

65-
plbi alle3isnxs, x0
66-
// CHECK-INST: plbi alle3isnxs, x0
67-
// CHECK-ENCODING: encoding: [0x00,0xab,0x0e,0xd5]
68-
// CHECK-ERROR: error: specified plbi op does not use a register
69-
// CHECK-UNKNOWN: d50eab00 sys #6, c10, c11, #0, x0
70-
71-
plbi alle3osnxs, x0
72-
// CHECK-INST: plbi alle3osnxs, x0
73-
// CHECK-ENCODING: encoding: [0x00,0xa9,0x0e,0xd5]
74-
// CHECK-ERROR: error: specified plbi op does not use a register
75-
// CHECK-UNKNOWN: d50ea900 sys #6, c10, c9, #0, x0
76-
7753
plbi alle2isnxs, x0
7854
// CHECK-INST: plbi alle2isnxs, x0
7955
// CHECK-ENCODING: encoding: [0x00,0xab,0x0c,0xd5]
@@ -109,9 +85,3 @@ plbi vmalle1osnxs, x0
10985
// CHECK-ENCODING: encoding: [0x00,0xa9,0x08,0xd5]
11086
// CHECK-ERROR: error: specified plbi op does not use a register
11187
// CHECK-UNKNOWN: d508a900 sys #0, c10, c9, #0, x0
112-
113-
plbi alle3is, x0
114-
// CHECK-INST: plbi alle3is, x0
115-
// CHECK-ENCODING: encoding: [0x00,0xa3,0x0e,0xd5]
116-
// CHECK-ERROR: error: specified plbi op does not use a register
117-
// CHECK-UNKNOWN: d50ea300 sys #6, c10, c3, #0, x0

‎llvm/test/MC/AArch64/arm-poe2.s‎

Lines changed: 24 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -2938,22 +2938,22 @@ tchangeb x1, #9, nB
29382938
// CHECK-ERROR: error: instruction requires: poe2
29392939

29402940

2941-
PLBI ALLE3
2942-
// CHECK-INST: plbi alle3
2943-
// CHECK-ENCODING: [0x1f,0xa7,0x0e,0xd5]
2944-
// CHECK-UNKNOWN: d50ea71f sys #6, c10, c7, #0
2941+
PLBI ALLE3, x3
2942+
// CHECK-INST: plbi alle3, x3
2943+
// CHECK-ENCODING: [0x03,0xa7,0x0e,0xd5]
2944+
// CHECK-UNKNOWN: d50ea703 sys #6, c10, c7, #0, x3
29452945
// CHECK-ERROR: error: PLBI ALLE3 requires: poe2
29462946

2947-
PLBI ALLE3IS
2948-
// CHECK-INST: plbi alle3is
2949-
// CHECK-ENCODING: [0x1f,0xa3,0x0e,0xd5]
2950-
// CHECK-UNKNOWN: d50ea31f sys #6, c10, c3, #0
2947+
PLBI ALLE3IS, x3
2948+
// CHECK-INST: plbi alle3is, x3
2949+
// CHECK-ENCODING: [0x03,0xa3,0x0e,0xd5]
2950+
// CHECK-UNKNOWN: d50ea303 sys #6, c10, c3, #0, x3
29512951
// CHECK-ERROR: error: PLBI ALLE3IS requires: poe2
29522952

2953-
PLBI ALLE3OS
2954-
// CHECK-INST: plbi alle3os
2955-
// CHECK-ENCODING: [0x1f,0xa1,0x0e,0xd5]
2956-
// CHECK-UNKNOWN: d50ea11f sys #6, c10, c1, #0
2953+
PLBI ALLE3OS, x3
2954+
// CHECK-INST: plbi alle3os, x3
2955+
// CHECK-ENCODING: [0x03,0xa1,0x0e,0xd5]
2956+
// CHECK-UNKNOWN: d50ea103 sys #6, c10, c1, #0, x3
29572957
// CHECK-ERROR: error: PLBI ALLE3OS requires: poe2
29582958

29592959
PLBI ALLE2
@@ -3082,22 +3082,22 @@ PLBI PERME1OS, X3
30823082
// CHECK-UNKNOWN: d508a123 sys #0, c10, c1, #1, x3
30833083
// CHECK-ERROR: error: PLBI PERME1OS requires: poe2
30843084

3085-
PLBI ALLE3NXS
3086-
// CHECK-INST: plbi alle3nxs
3087-
// CHECK-ENCODING: [0x1f,0xaf,0x0e,0xd5]
3088-
// CHECK-UNKNOWN: d50eaf1f sys #6, c10, c15, #0
3085+
PLBI ALLE3NXS, X3
3086+
// CHECK-INST: plbi alle3nxs, x3
3087+
// CHECK-ENCODING: [0x03,0xaf,0x0e,0xd5]
3088+
// CHECK-UNKNOWN: d50eaf03 sys #6, c10, c15, #0, x3
30893089
// CHECK-ERROR: error: PLBI ALLE3NXS requires: poe2
30903090

3091-
PLBI ALLE3ISNXS
3092-
// CHECK-INST: plbi alle3isnxs
3093-
// CHECK-ENCODING: [0x1f,0xab,0x0e,0xd5]
3094-
// CHECK-UNKNOWN: d50eab1f sys #6, c10, c11, #0
3091+
PLBI ALLE3ISNXS, X3
3092+
// CHECK-INST: plbi alle3isnxs, x3
3093+
// CHECK-ENCODING: [0x03,0xab,0x0e,0xd5]
3094+
// CHECK-UNKNOWN: d50eab03 sys #6, c10, c11, #0, x3
30953095
// CHECK-ERROR: error: PLBI ALLE3ISNXS requires: poe2
30963096

3097-
PLBI ALLE3OSNXS
3098-
// CHECK-INST: plbi alle3osnxs
3099-
// CHECK-ENCODING: [0x1f,0xa9,0x0e,0xd5]
3100-
// CHECK-UNKNOWN: d50ea91f sys #6, c10, c9, #0
3097+
PLBI ALLE3OSNXS, X3
3098+
// CHECK-INST: plbi alle3osnxs, x3
3099+
// CHECK-ENCODING: [0x03,0xa9,0x0e,0xd5]
3100+
// CHECK-UNKNOWN: d50ea903 sys #6, c10, c9, #0, x3
31013101
// CHECK-ERROR: error: PLBI ALLE3OSNXS requires: poe2
31023102

31033103
PLBI ALLE2NXS

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