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wangpc-ppwangpc-pp
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[RISCV] Enable bidirectional postra scheduling
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1,011 files changed

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‎llvm/lib/Target/RISCV/RISCVSubtarget.cpp‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,7 @@
1616
#include "RISCV.h"
1717
#include "RISCVFrameLowering.h"
1818
#include "RISCVTargetMachine.h"
19+
#include "llvm/CodeGen/MachineScheduler.h"
1920
#include "llvm/CodeGen/MacroFusion.h"
2021
#include "llvm/CodeGen/ScheduleDAGMutation.h"
2122
#include "llvm/MC/TargetRegistry.h"
@@ -199,3 +200,11 @@ unsigned RISCVSubtarget::getMinimumJumpTableEntries() const {
199200
? RISCVMinimumJumpTableEntries
200201
: TuneInfo->MinimumJumpTableEntries;
201202
}
203+
204+
void RISCVSubtarget::overridePostRASchedPolicy(MachineSchedPolicy &Policy,
205+
unsigned NumRegionInstrs) const {
206+
// Do bidirectional scheduling since it provides a more balanced scheduling
207+
// leading to better performance. This will increase compile time.
208+
Policy.OnlyTopDown = false;
209+
Policy.OnlyBottomUp = false;
210+
}

‎llvm/lib/Target/RISCV/RISCVSubtarget.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -330,6 +330,9 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
330330
unsigned getTailDupAggressiveThreshold() const {
331331
return TuneInfo->TailDupAggressiveThreshold;
332332
}
333+
334+
void overridePostRASchedPolicy(MachineSchedPolicy &Policy,
335+
unsigned NumRegionInstrs) const override;
333336
};
334337
} // End llvm namespace
335338

‎llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll‎

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -26,17 +26,17 @@ define i32 @add_i8_signext_i32(i8 %a, i8 %b) {
2626
; RV32IM: # %bb.0: # %entry
2727
; RV32IM-NEXT: slli a0, a0, 24
2828
; RV32IM-NEXT: slli a1, a1, 24
29-
; RV32IM-NEXT: srai a0, a0, 24
3029
; RV32IM-NEXT: srai a1, a1, 24
30+
; RV32IM-NEXT: srai a0, a0, 24
3131
; RV32IM-NEXT: add a0, a0, a1
3232
; RV32IM-NEXT: ret
3333
;
3434
; RV64IM-LABEL: add_i8_signext_i32:
3535
; RV64IM: # %bb.0: # %entry
3636
; RV64IM-NEXT: slli a0, a0, 56
3737
; RV64IM-NEXT: slli a1, a1, 56
38-
; RV64IM-NEXT: srai a0, a0, 56
3938
; RV64IM-NEXT: srai a1, a1, 56
39+
; RV64IM-NEXT: srai a0, a0, 56
4040
; RV64IM-NEXT: add a0, a0, a1
4141
; RV64IM-NEXT: ret
4242
entry:
@@ -49,15 +49,15 @@ entry:
4949
define i32 @add_i8_zeroext_i32(i8 %a, i8 %b) {
5050
; RV32IM-LABEL: add_i8_zeroext_i32:
5151
; RV32IM: # %bb.0: # %entry
52-
; RV32IM-NEXT: andi a0, a0, 255
5352
; RV32IM-NEXT: andi a1, a1, 255
53+
; RV32IM-NEXT: andi a0, a0, 255
5454
; RV32IM-NEXT: add a0, a0, a1
5555
; RV32IM-NEXT: ret
5656
;
5757
; RV64IM-LABEL: add_i8_zeroext_i32:
5858
; RV64IM: # %bb.0: # %entry
59-
; RV64IM-NEXT: andi a0, a0, 255
6059
; RV64IM-NEXT: andi a1, a1, 255
60+
; RV64IM-NEXT: andi a0, a0, 255
6161
; RV64IM-NEXT: add a0, a0, a1
6262
; RV64IM-NEXT: ret
6363
entry:
@@ -404,8 +404,8 @@ define i64 @add_i64(i64 %a, i64 %b) {
404404
; RV32IM-LABEL: add_i64:
405405
; RV32IM: # %bb.0: # %entry
406406
; RV32IM-NEXT: add a0, a0, a2
407-
; RV32IM-NEXT: sltu a2, a0, a2
408407
; RV32IM-NEXT: add a1, a1, a3
408+
; RV32IM-NEXT: sltu a2, a0, a2
409409
; RV32IM-NEXT: add a1, a1, a2
410410
; RV32IM-NEXT: ret
411411
;
@@ -439,8 +439,8 @@ define i64 @sub_i64(i64 %a, i64 %b) {
439439
; RV32IM-LABEL: sub_i64:
440440
; RV32IM: # %bb.0: # %entry
441441
; RV32IM-NEXT: sub a4, a0, a2
442-
; RV32IM-NEXT: sltu a0, a0, a2
443442
; RV32IM-NEXT: sub a1, a1, a3
443+
; RV32IM-NEXT: sltu a0, a0, a2
444444
; RV32IM-NEXT: sub a1, a1, a0
445445
; RV32IM-NEXT: mv a0, a4
446446
; RV32IM-NEXT: ret
@@ -460,8 +460,8 @@ define i64 @subi_i64(i64 %a) {
460460
; RV32IM-NEXT: lui a2, 1048275
461461
; RV32IM-NEXT: addi a2, a2, -1548
462462
; RV32IM-NEXT: add a0, a0, a2
463-
; RV32IM-NEXT: sltu a2, a0, a2
464463
; RV32IM-NEXT: addi a1, a1, -1
464+
; RV32IM-NEXT: sltu a2, a0, a2
465465
; RV32IM-NEXT: add a1, a1, a2
466466
; RV32IM-NEXT: ret
467467
;
@@ -480,8 +480,8 @@ define i64 @neg_i64(i64 %a) {
480480
; RV32IM-LABEL: neg_i64:
481481
; RV32IM: # %bb.0: # %entry
482482
; RV32IM-NEXT: neg a2, a0
483-
; RV32IM-NEXT: snez a0, a0
484483
; RV32IM-NEXT: neg a1, a1
484+
; RV32IM-NEXT: snez a0, a0
485485
; RV32IM-NEXT: sub a1, a1, a0
486486
; RV32IM-NEXT: mv a0, a2
487487
; RV32IM-NEXT: ret
@@ -500,8 +500,8 @@ entry:
500500
define i64 @and_i64(i64 %a, i64 %b) {
501501
; RV32IM-LABEL: and_i64:
502502
; RV32IM: # %bb.0: # %entry
503-
; RV32IM-NEXT: and a0, a0, a2
504503
; RV32IM-NEXT: and a1, a1, a3
504+
; RV32IM-NEXT: and a0, a0, a2
505505
; RV32IM-NEXT: ret
506506
;
507507
; RV64IM-LABEL: and_i64:
@@ -516,8 +516,8 @@ entry:
516516
define i64 @andi_i64(i64 %a) {
517517
; RV32IM-LABEL: andi_i64:
518518
; RV32IM: # %bb.0: # %entry
519-
; RV32IM-NEXT: andi a0, a0, 1234
520519
; RV32IM-NEXT: li a1, 0
520+
; RV32IM-NEXT: andi a0, a0, 1234
521521
; RV32IM-NEXT: ret
522522
;
523523
; RV64IM-LABEL: andi_i64:
@@ -532,8 +532,8 @@ entry:
532532
define i64 @or_i64(i64 %a, i64 %b) {
533533
; RV32IM-LABEL: or_i64:
534534
; RV32IM: # %bb.0: # %entry
535-
; RV32IM-NEXT: or a0, a0, a2
536535
; RV32IM-NEXT: or a1, a1, a3
536+
; RV32IM-NEXT: or a0, a0, a2
537537
; RV32IM-NEXT: ret
538538
;
539539
; RV64IM-LABEL: or_i64:
@@ -563,8 +563,8 @@ entry:
563563
define i64 @xor_i64(i64 %a, i64 %b) {
564564
; RV32IM-LABEL: xor_i64:
565565
; RV32IM: # %bb.0: # %entry
566-
; RV32IM-NEXT: xor a0, a0, a2
567566
; RV32IM-NEXT: xor a1, a1, a3
567+
; RV32IM-NEXT: xor a0, a0, a2
568568
; RV32IM-NEXT: ret
569569
;
570570
; RV64IM-LABEL: xor_i64:
@@ -594,11 +594,11 @@ entry:
594594
define i64 @mul_i64(i64 %a, i64 %b) {
595595
; RV32IM-LABEL: mul_i64:
596596
; RV32IM: # %bb.0: # %entry
597+
; RV32IM-NEXT: mul a4, a0, a2
597598
; RV32IM-NEXT: mul a1, a1, a2
598599
; RV32IM-NEXT: mul a3, a0, a3
599-
; RV32IM-NEXT: mul a4, a0, a2
600-
; RV32IM-NEXT: mulhu a0, a0, a2
601600
; RV32IM-NEXT: add a1, a1, a3
601+
; RV32IM-NEXT: mulhu a0, a0, a2
602602
; RV32IM-NEXT: add a1, a1, a0
603603
; RV32IM-NEXT: mv a0, a4
604604
; RV32IM-NEXT: ret

‎llvm/test/CodeGen/RISCV/GlobalISel/bitmanip.ll‎

Lines changed: 32 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -7,17 +7,17 @@ define i2 @bitreverse_i2(i2 %x) {
77
; RV32: # %bb.0:
88
; RV32-NEXT: slli a1, a0, 1
99
; RV32-NEXT: andi a0, a0, 3
10-
; RV32-NEXT: andi a1, a1, 2
1110
; RV32-NEXT: srli a0, a0, 1
11+
; RV32-NEXT: andi a1, a1, 2
1212
; RV32-NEXT: or a0, a1, a0
1313
; RV32-NEXT: ret
1414
;
1515
; RV64-LABEL: bitreverse_i2:
1616
; RV64: # %bb.0:
1717
; RV64-NEXT: slli a1, a0, 1
1818
; RV64-NEXT: andi a0, a0, 3
19-
; RV64-NEXT: andi a1, a1, 2
2019
; RV64-NEXT: srli a0, a0, 1
20+
; RV64-NEXT: andi a1, a1, 2
2121
; RV64-NEXT: or a0, a1, a0
2222
; RV64-NEXT: ret
2323
%rev = call i2 @llvm.bitreverse.i2(i2 %x)
@@ -28,22 +28,22 @@ define i3 @bitreverse_i3(i3 %x) {
2828
; RV32-LABEL: bitreverse_i3:
2929
; RV32: # %bb.0:
3030
; RV32-NEXT: slli a1, a0, 2
31-
; RV32-NEXT: andi a0, a0, 7
3231
; RV32-NEXT: andi a1, a1, 4
32+
; RV32-NEXT: andi a0, a0, 7
3333
; RV32-NEXT: andi a2, a0, 2
34-
; RV32-NEXT: or a1, a1, a2
3534
; RV32-NEXT: srli a0, a0, 2
35+
; RV32-NEXT: or a1, a1, a2
3636
; RV32-NEXT: or a0, a1, a0
3737
; RV32-NEXT: ret
3838
;
3939
; RV64-LABEL: bitreverse_i3:
4040
; RV64: # %bb.0:
4141
; RV64-NEXT: slli a1, a0, 2
42-
; RV64-NEXT: andi a0, a0, 7
4342
; RV64-NEXT: andi a1, a1, 4
43+
; RV64-NEXT: andi a0, a0, 7
4444
; RV64-NEXT: andi a2, a0, 2
45-
; RV64-NEXT: or a1, a1, a2
4645
; RV64-NEXT: srli a0, a0, 2
46+
; RV64-NEXT: or a1, a1, a2
4747
; RV64-NEXT: or a0, a1, a0
4848
; RV64-NEXT: ret
4949
%rev = call i3 @llvm.bitreverse.i3(i3 %x)
@@ -54,30 +54,30 @@ define i4 @bitreverse_i4(i4 %x) {
5454
; RV32-LABEL: bitreverse_i4:
5555
; RV32: # %bb.0:
5656
; RV32-NEXT: slli a1, a0, 3
57-
; RV32-NEXT: slli a2, a0, 1
5857
; RV32-NEXT: andi a1, a1, 8
58+
; RV32-NEXT: slli a2, a0, 1
5959
; RV32-NEXT: andi a2, a2, 4
60-
; RV32-NEXT: andi a0, a0, 15
6160
; RV32-NEXT: or a1, a1, a2
61+
; RV32-NEXT: andi a0, a0, 15
6262
; RV32-NEXT: srli a2, a0, 1
6363
; RV32-NEXT: andi a2, a2, 2
64-
; RV32-NEXT: or a1, a1, a2
6564
; RV32-NEXT: srli a0, a0, 3
65+
; RV32-NEXT: or a1, a1, a2
6666
; RV32-NEXT: or a0, a1, a0
6767
; RV32-NEXT: ret
6868
;
6969
; RV64-LABEL: bitreverse_i4:
7070
; RV64: # %bb.0:
7171
; RV64-NEXT: slli a1, a0, 3
72-
; RV64-NEXT: slli a2, a0, 1
7372
; RV64-NEXT: andi a1, a1, 8
73+
; RV64-NEXT: slli a2, a0, 1
7474
; RV64-NEXT: andi a2, a2, 4
75-
; RV64-NEXT: andi a0, a0, 15
7675
; RV64-NEXT: or a1, a1, a2
76+
; RV64-NEXT: andi a0, a0, 15
7777
; RV64-NEXT: srli a2, a0, 1
7878
; RV64-NEXT: andi a2, a2, 2
79-
; RV64-NEXT: or a1, a1, a2
8079
; RV64-NEXT: srli a0, a0, 3
80+
; RV64-NEXT: or a1, a1, a2
8181
; RV64-NEXT: or a0, a1, a0
8282
; RV64-NEXT: ret
8383
%rev = call i4 @llvm.bitreverse.i4(i4 %x)
@@ -88,46 +88,46 @@ define i7 @bitreverse_i7(i7 %x) {
8888
; RV32-LABEL: bitreverse_i7:
8989
; RV32: # %bb.0:
9090
; RV32-NEXT: slli a1, a0, 6
91-
; RV32-NEXT: slli a2, a0, 4
9291
; RV32-NEXT: andi a1, a1, 64
92+
; RV32-NEXT: slli a2, a0, 4
9393
; RV32-NEXT: andi a2, a2, 32
9494
; RV32-NEXT: or a1, a1, a2
9595
; RV32-NEXT: slli a2, a0, 2
96-
; RV32-NEXT: andi a0, a0, 127
9796
; RV32-NEXT: andi a2, a2, 16
97+
; RV32-NEXT: andi a0, a0, 127
9898
; RV32-NEXT: andi a3, a0, 8
9999
; RV32-NEXT: or a2, a2, a3
100100
; RV32-NEXT: or a1, a1, a2
101101
; RV32-NEXT: srli a2, a0, 2
102-
; RV32-NEXT: srli a3, a0, 4
103102
; RV32-NEXT: andi a2, a2, 4
103+
; RV32-NEXT: srli a3, a0, 4
104104
; RV32-NEXT: andi a3, a3, 2
105105
; RV32-NEXT: or a2, a2, a3
106-
; RV32-NEXT: or a1, a1, a2
107106
; RV32-NEXT: srli a0, a0, 6
107+
; RV32-NEXT: or a1, a1, a2
108108
; RV32-NEXT: or a0, a1, a0
109109
; RV32-NEXT: ret
110110
;
111111
; RV64-LABEL: bitreverse_i7:
112112
; RV64: # %bb.0:
113113
; RV64-NEXT: slli a1, a0, 6
114-
; RV64-NEXT: slli a2, a0, 4
115114
; RV64-NEXT: andi a1, a1, 64
115+
; RV64-NEXT: slli a2, a0, 4
116116
; RV64-NEXT: andi a2, a2, 32
117117
; RV64-NEXT: or a1, a1, a2
118118
; RV64-NEXT: slli a2, a0, 2
119-
; RV64-NEXT: andi a0, a0, 127
120119
; RV64-NEXT: andi a2, a2, 16
120+
; RV64-NEXT: andi a0, a0, 127
121121
; RV64-NEXT: andi a3, a0, 8
122122
; RV64-NEXT: or a2, a2, a3
123123
; RV64-NEXT: or a1, a1, a2
124124
; RV64-NEXT: srli a2, a0, 2
125-
; RV64-NEXT: srli a3, a0, 4
126125
; RV64-NEXT: andi a2, a2, 4
126+
; RV64-NEXT: srli a3, a0, 4
127127
; RV64-NEXT: andi a3, a3, 2
128128
; RV64-NEXT: or a2, a2, a3
129-
; RV64-NEXT: or a1, a1, a2
130129
; RV64-NEXT: srli a0, a0, 6
130+
; RV64-NEXT: or a1, a1, a2
131131
; RV64-NEXT: or a0, a1, a0
132132
; RV64-NEXT: ret
133133
%rev = call i7 @llvm.bitreverse.i7(i7 %x)
@@ -137,69 +137,69 @@ define i7 @bitreverse_i7(i7 %x) {
137137
define i24 @bitreverse_i24(i24 %x) {
138138
; RV32-LABEL: bitreverse_i24:
139139
; RV32: # %bb.0:
140+
; RV32-NEXT: slli a1, a0, 16
140141
; RV32-NEXT: lui a2, 4096
141142
; RV32-NEXT: addi a2, a2, -1
142-
; RV32-NEXT: slli a1, a0, 16
143143
; RV32-NEXT: and a0, a0, a2
144144
; RV32-NEXT: srli a0, a0, 16
145145
; RV32-NEXT: or a0, a0, a1
146146
; RV32-NEXT: lui a1, 1048335
147147
; RV32-NEXT: addi a1, a1, 240
148148
; RV32-NEXT: and a3, a1, a2
149149
; RV32-NEXT: and a3, a0, a3
150+
; RV32-NEXT: srli a3, a3, 4
150151
; RV32-NEXT: slli a0, a0, 4
151152
; RV32-NEXT: and a0, a0, a1
153+
; RV32-NEXT: or a0, a3, a0
152154
; RV32-NEXT: lui a1, 1047757
153-
; RV32-NEXT: srli a3, a3, 4
154155
; RV32-NEXT: addi a1, a1, -820
155-
; RV32-NEXT: or a0, a3, a0
156156
; RV32-NEXT: and a3, a1, a2
157157
; RV32-NEXT: and a3, a0, a3
158+
; RV32-NEXT: srli a3, a3, 2
158159
; RV32-NEXT: slli a0, a0, 2
159160
; RV32-NEXT: and a0, a0, a1
161+
; RV32-NEXT: or a0, a3, a0
160162
; RV32-NEXT: lui a1, 1047211
161-
; RV32-NEXT: srli a3, a3, 2
162163
; RV32-NEXT: addi a1, a1, -1366
163-
; RV32-NEXT: or a0, a3, a0
164164
; RV32-NEXT: and a2, a1, a2
165165
; RV32-NEXT: and a2, a0, a2
166166
; RV32-NEXT: slli a0, a0, 1
167-
; RV32-NEXT: srli a2, a2, 1
168167
; RV32-NEXT: and a0, a0, a1
168+
; RV32-NEXT: srli a2, a2, 1
169169
; RV32-NEXT: or a0, a2, a0
170170
; RV32-NEXT: ret
171171
;
172172
; RV64-LABEL: bitreverse_i24:
173173
; RV64: # %bb.0:
174+
; RV64-NEXT: slli a1, a0, 16
174175
; RV64-NEXT: lui a2, 4096
175176
; RV64-NEXT: addiw a2, a2, -1
176-
; RV64-NEXT: slli a1, a0, 16
177177
; RV64-NEXT: and a0, a0, a2
178178
; RV64-NEXT: srli a0, a0, 16
179179
; RV64-NEXT: or a0, a0, a1
180180
; RV64-NEXT: lui a1, 1048335
181181
; RV64-NEXT: addiw a1, a1, 240
182182
; RV64-NEXT: and a3, a1, a2
183183
; RV64-NEXT: and a3, a0, a3
184+
; RV64-NEXT: srli a3, a3, 4
184185
; RV64-NEXT: slli a0, a0, 4
185186
; RV64-NEXT: and a0, a0, a1
187+
; RV64-NEXT: or a0, a3, a0
186188
; RV64-NEXT: lui a1, 1047757
187-
; RV64-NEXT: srli a3, a3, 4
188189
; RV64-NEXT: addiw a1, a1, -820
189-
; RV64-NEXT: or a0, a3, a0
190190
; RV64-NEXT: and a3, a1, a2
191191
; RV64-NEXT: and a3, a0, a3
192+
; RV64-NEXT: srli a3, a3, 2
192193
; RV64-NEXT: slli a0, a0, 2
193194
; RV64-NEXT: and a0, a0, a1
195+
; RV64-NEXT: or a0, a3, a0
194196
; RV64-NEXT: lui a1, 1047211
195-
; RV64-NEXT: srli a3, a3, 2
196197
; RV64-NEXT: addiw a1, a1, -1366
197-
; RV64-NEXT: or a0, a3, a0
198198
; RV64-NEXT: and a2, a1, a2
199199
; RV64-NEXT: and a2, a0, a2
200200
; RV64-NEXT: slli a0, a0, 1
201-
; RV64-NEXT: srli a2, a2, 1
202201
; RV64-NEXT: and a0, a0, a1
202+
; RV64-NEXT: srli a2, a2, 1
203203
; RV64-NEXT: or a0, a2, a0
204204
; RV64-NEXT: ret
205205
%rev = call i24 @llvm.bitreverse.i24(i24 %x)

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