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‎llvm/test/CodeGen/AArch64/veclib-llvm.sincospi.ll‎

Lines changed: 59 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,25 @@
1-
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --filter "(bl|ptrue)" --version 5
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=aarch64-gnu-linux -mattr=+neon,+sve -vector-library=sleefgnuabi < %s | FileCheck %s -check-prefix=SLEEF
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; RUN: llc -mtriple=aarch64-gnu-linux -mattr=+neon,+sve -vector-library=ArmPL < %s | FileCheck %s -check-prefix=ARMPL
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define void @test_sincospi_v4f32(<4 x float> %x, ptr noalias %out_sin, ptr noalias %out_cos) {
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; SLEEF-LABEL: test_sincospi_v4f32:
7-
; SLEEF: bl _ZGVnN4vl4l4_sincospif
7+
; SLEEF: // %bb.0:
8+
; SLEEF-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
9+
; SLEEF-NEXT: .cfi_def_cfa_offset 16
10+
; SLEEF-NEXT: .cfi_offset w30, -16
11+
; SLEEF-NEXT: bl _ZGVnN4vl4l4_sincospif
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; SLEEF-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
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; SLEEF-NEXT: ret
814
;
915
; ARMPL-LABEL: test_sincospi_v4f32:
10-
; ARMPL: bl armpl_vsincospiq_f32
16+
; ARMPL: // %bb.0:
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; ARMPL-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
18+
; ARMPL-NEXT: .cfi_def_cfa_offset 16
19+
; ARMPL-NEXT: .cfi_offset w30, -16
20+
; ARMPL-NEXT: bl armpl_vsincospiq_f32
21+
; ARMPL-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
22+
; ARMPL-NEXT: ret
1123
%result = call { <4 x float>, <4 x float> } @llvm.sincospi.v4f32(<4 x float> %x)
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%result.0 = extractvalue { <4 x float>, <4 x float> } %result, 0
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%result.1 = extractvalue { <4 x float>, <4 x float> } %result, 1
@@ -18,10 +30,22 @@ define void @test_sincospi_v4f32(<4 x float> %x, ptr noalias %out_sin, ptr noali
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define void @test_sincospi_v2f64(<2 x double> %x, ptr noalias %out_sin, ptr noalias %out_cos) {
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; SLEEF-LABEL: test_sincospi_v2f64:
21-
; SLEEF: bl _ZGVnN2vl8l8_sincospi
33+
; SLEEF: // %bb.0:
34+
; SLEEF-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
35+
; SLEEF-NEXT: .cfi_def_cfa_offset 16
36+
; SLEEF-NEXT: .cfi_offset w30, -16
37+
; SLEEF-NEXT: bl _ZGVnN2vl8l8_sincospi
38+
; SLEEF-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
39+
; SLEEF-NEXT: ret
2240
;
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; ARMPL-LABEL: test_sincospi_v2f64:
24-
; ARMPL: bl armpl_vsincospiq_f64
42+
; ARMPL: // %bb.0:
43+
; ARMPL-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
44+
; ARMPL-NEXT: .cfi_def_cfa_offset 16
45+
; ARMPL-NEXT: .cfi_offset w30, -16
46+
; ARMPL-NEXT: bl armpl_vsincospiq_f64
47+
; ARMPL-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
48+
; ARMPL-NEXT: ret
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%result = call { <2 x double>, <2 x double> } @llvm.sincospi.v2f64(<2 x double> %x)
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%result.0 = extractvalue { <2 x double>, <2 x double> } %result, 0
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%result.1 = extractvalue { <2 x double>, <2 x double> } %result, 1
@@ -32,11 +56,23 @@ define void @test_sincospi_v2f64(<2 x double> %x, ptr noalias %out_sin, ptr noal
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define void @test_sincospi_nxv4f32(<vscale x 4 x float> %x, ptr noalias %out_sin, ptr noalias %out_cos) {
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; SLEEF-LABEL: test_sincospi_nxv4f32:
35-
; SLEEF: bl _ZGVsNxvl4l4_sincospif
59+
; SLEEF: // %bb.0:
60+
; SLEEF-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
61+
; SLEEF-NEXT: .cfi_def_cfa_offset 16
62+
; SLEEF-NEXT: .cfi_offset w30, -16
63+
; SLEEF-NEXT: bl _ZGVsNxvl4l4_sincospif
64+
; SLEEF-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
65+
; SLEEF-NEXT: ret
3666
;
3767
; ARMPL-LABEL: test_sincospi_nxv4f32:
38-
; ARMPL: ptrue p0.s
39-
; ARMPL: bl armpl_svsincospi_f32_x
68+
; ARMPL: // %bb.0:
69+
; ARMPL-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
70+
; ARMPL-NEXT: .cfi_def_cfa_offset 16
71+
; ARMPL-NEXT: .cfi_offset w30, -16
72+
; ARMPL-NEXT: ptrue p0.s
73+
; ARMPL-NEXT: bl armpl_svsincospi_f32_x
74+
; ARMPL-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
75+
; ARMPL-NEXT: ret
4076
%result = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.sincospi.nxv4f32(<vscale x 4 x float> %x)
4177
%result.0 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %result, 0
4278
%result.1 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %result, 1
@@ -47,11 +83,23 @@ define void @test_sincospi_nxv4f32(<vscale x 4 x float> %x, ptr noalias %out_sin
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4884
define void @test_sincospi_nxv2f64(<vscale x 2 x double> %x, ptr noalias %out_sin, ptr noalias %out_cos) {
4985
; SLEEF-LABEL: test_sincospi_nxv2f64:
50-
; SLEEF: bl _ZGVsNxvl8l8_sincospi
86+
; SLEEF: // %bb.0:
87+
; SLEEF-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
88+
; SLEEF-NEXT: .cfi_def_cfa_offset 16
89+
; SLEEF-NEXT: .cfi_offset w30, -16
90+
; SLEEF-NEXT: bl _ZGVsNxvl8l8_sincospi
91+
; SLEEF-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
92+
; SLEEF-NEXT: ret
5193
;
5294
; ARMPL-LABEL: test_sincospi_nxv2f64:
53-
; ARMPL: ptrue p0.d
54-
; ARMPL: bl armpl_svsincospi_f64_x
95+
; ARMPL: // %bb.0:
96+
; ARMPL-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
97+
; ARMPL-NEXT: .cfi_def_cfa_offset 16
98+
; ARMPL-NEXT: .cfi_offset w30, -16
99+
; ARMPL-NEXT: ptrue p0.d
100+
; ARMPL-NEXT: bl armpl_svsincospi_f64_x
101+
; ARMPL-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
102+
; ARMPL-NEXT: ret
55103
%result = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.sincospi.nxv2f64(<vscale x 2 x double> %x)
56104
%result.0 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %result, 0
57105
%result.1 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %result, 1

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