Make implementation more close to GLIBC

spavloff · spavloff · commit f62c7d4603dc · 2025-07-15T12:31:23.000+07:00
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -14021,7 +14021,6 @@ SDValue RISCVTargetLowering::lowerGET_FPMODE(SDValue Op,
   SDVTList VTs = DAG.getVTList(XLenVT, MVT::Other);
   SDValue Result = DAG.getNode(RISCVISD::READ_CSR, DL, VTs, Chain, SysRegNo);
   Chain = Result.getValue(1);
-  Result = DAG.getNode(ISD::AND, DL, XLenVT, Result, ModeMask);
   return DAG.getMergeValues({Result, Chain}, DL);
 }
 
diff --git a/llvm/test/CodeGen/RISCV/fpenv-xlen.ll b/llvm/test/CodeGen/RISCV/fpenv-xlen.ll
@@ -40,7 +40,6 @@ define iXLen @func_get_fpmode() {
 ; CHECK-LABEL: func_get_fpmode:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    frcsr a0
-; CHECK-NEXT:    andi  a0, a0, -32
 ; CHECK-NEXT:    ret
 entry:
   %fpenv = call iXLen @llvm.get.fpmode.iXLen()

Original file line number	Diff line number	Diff line change
`@@ -14021,7 +14021,6 @@ SDValue RISCVTargetLowering::lowerGET_FPMODE(SDValue Op,`
`14021`	`14021`	`SDVTList VTs = DAG.getVTList(XLenVT, MVT::Other);`
`14022`	`14022`	`SDValue Result = DAG.getNode(RISCVISD::READ_CSR, DL, VTs, Chain, SysRegNo);`
`14023`	`14023`	`Chain = Result.getValue(1);`
`14024`		`- Result = DAG.getNode(ISD::AND, DL, XLenVT, Result, ModeMask);`
`14025`	`14024`	`return DAG.getMergeValues({Result, Chain}, DL);`
`14026`	`14025`	`}`
`14027`	`14026`