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Vasileios Porpodas
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[Spill2Reg] MBB live-ins are now being updated
This patch implements updates for the MBB live-ins due to the newly introduced instructions emitted by spill2reg. This is required for correct tracking of live register usage. Original review: https://reviews.llvm.org/D118304
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‎llvm/lib/CodeGen/Spill2Reg.cpp‎

Lines changed: 96 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -66,11 +66,43 @@ class Spill2Reg : public MachineFunctionPass {
6666
/// differs across accesses to the same stack slot.
6767
unsigned SpillBits = 0;
6868
#ifndef NDEBUG
69-
LLVM_DUMP_METHOD void dump() const;
69+
LLVM_DUMP_METHOD virtual void dump() const;
70+
virtual ~MIData() {}
71+
#endif
72+
};
73+
74+
struct MIDataWithLiveIn : public MIData {
75+
MIDataWithLiveIn(MachineInstr *MI, const MachineOperand *MO,
76+
unsigned SpillBits)
77+
: MIData(MI, MO, SpillBits) {}
78+
/// We set this to false to mark the vector register associated to this
79+
/// reload as definitely not live-in. This is useful in blocks with both
80+
/// spill and reload of the same stack slot, like in the example:
81+
/// \verbatim
82+
/// bb:
83+
/// spill %stack.0
84+
/// reload %stack.0
85+
/// \endverbatim
86+
/// This information is used during `updateLiveIns()`. We are collecting
87+
/// this information during `collectSpillsAndReloads()` because we are
88+
/// already walking through the code there. Otherwise we would need to
89+
/// walk throught the code again in `updateLiveIns()` just to check for
90+
/// other spills in the block, which would waste compilation time.
91+
bool IsLiveIn = true;
92+
#ifndef NDEBUG
93+
LLVM_DUMP_METHOD virtual void dump() const override;
7094
#endif
7195
};
7296
SmallVector<MIData, 1> Spills;
73-
SmallVector<MIData, 1> Reloads;
97+
SmallVector<MIDataWithLiveIn, 1> Reloads;
98+
99+
/// \Returns the register class of the register being spilled.
100+
const TargetRegisterClass *
101+
getSpilledRegClass(const TargetInstrInfo *TII,
102+
const TargetRegisterInfo *TRI) const {
103+
auto Reg0 = Spills.front().MO->getReg();
104+
return TII->getVectorRegisterClassForSpill2Reg(TRI, Reg0);
105+
}
74106

75107
/// \Returns the register class of the register being spilled.
76108
const TargetRegisterClass *
@@ -195,6 +227,15 @@ void Spill2Reg::collectSpillsAndReloads() {
195227
}
196228
unsigned SpillBits = TRI->getRegSizeInBits(MO->getReg(), *MRI);
197229
Entry.Spills.emplace_back(Spill, MO, SpillBits);
230+
231+
// If any of the reloads collected so far is in the same MBB then mark
232+
// it as non live-in. This is used in `updateLiveIns()` where we update
233+
// the liveins of MBBs to include the new vector register. Doing this
234+
// now avoids an MBB walk in `updateLiveIns()` which should save
235+
// compilation time.
236+
for (auto &MID : Entry.Reloads)
237+
if (MID.MI->getParent() == &MBB)
238+
MID.IsLiveIn = false;
198239
} else if (const MachineOperand *MO =
199240
TII->isLoadFromStackSlotMO(MI, StackSlot)) {
200241
MachineInstr *Reload = &MI;
@@ -265,6 +306,49 @@ static void DFS(MachineBasicBlock *MBB, DenseSet<MachineBasicBlock *> &Visited,
265306
for (MachineBasicBlock *PredMBB : MBB->predecessors())
266307
DFS(PredMBB, Visited, Fn);
267308
}
309+
310+
void Spill2Reg::updateLiveIns(StackSlotDataEntry &Entry, MCRegister VectorReg) {
311+
// Collect the parent MBBs of Spills for fast lookup.
312+
DenseSet<MachineBasicBlock *> SpillMBBs(Entry.Spills.size());
313+
DenseSet<MachineInstr *> Spills(Entry.Spills.size());
314+
for (const auto &Data : Entry.Spills) {
315+
SpillMBBs.insert(Data.MI->getParent());
316+
Spills.insert(Data.MI);
317+
}
318+
319+
auto AddLiveInIfRequired = [VectorReg, &SpillMBBs](MachineBasicBlock *MBB) {
320+
// If there is a spill in this MBB then we don't need to add a live-in.
321+
// This works even if there is a reload above the spill, like this:
322+
// reload stack.0
323+
// spill stack.0
324+
// because the live-in due to the reload is handled at a separate walk.
325+
if (SpillMBBs.count(MBB))
326+
// Return true to stop the recursion.
327+
return true;
328+
// If there are no spills in this block then the register is live-in.
329+
if (!MBB->isLiveIn(VectorReg))
330+
MBB->addLiveIn(VectorReg);
331+
// Return false to continue the recursion.
332+
return false;
333+
};
334+
335+
// Update the MBB live-ins. These are used for the live regs calculation.
336+
DenseSet<MachineBasicBlock *> Visited;
337+
for (const auto &ReloadData : Entry.Reloads) {
338+
MachineInstr *Reload = ReloadData.MI;
339+
MachineBasicBlock *MBB = Reload->getParent();
340+
// From a previous walk in MBB we know whether the reload is live-in, or
341+
// whether the value comes from an earlier spill in the same MBB.
342+
if (!ReloadData.IsLiveIn)
343+
continue;
344+
if (!MBB->isLiveIn(VectorReg))
345+
MBB->addLiveIn(VectorReg);
346+
347+
for (MachineBasicBlock *PredMBB : Reload->getParent()->predecessors())
348+
DFS(PredMBB, Visited, AddLiveInIfRequired);
349+
}
350+
}
351+
268352
// Replace stack-based spills/reloads with register-based ones.
269353
void Spill2Reg::replaceStackWithReg(StackSlotDataEntry &Entry,
270354
Register VectorReg) {
@@ -408,6 +492,12 @@ void Spill2Reg::generateCode() {
408492
if (!PhysVectorRegOpt)
409493
continue;
410494

495+
// Update the MBB live-ins. These are used for the live regs calculation.
496+
// Collect the parent MBBs of Spills for fast lookup.
497+
// NOTE: We do that before calling replaceStackWithReg() because it will
498+
// remove the spill/reload instructions from Entry.
499+
updateLiveIns(Entry, *PhysVectorRegOpt);
500+
411501
// Replace stack accesses with register accesses.
412502
replaceStackWithReg(Entry, *PhysVectorRegOpt);
413503

@@ -437,6 +527,10 @@ void Spill2Reg::StackSlotDataEntry::MIData::dump() const {
437527
dbgs() << " (" << *MO << ") " << *MI;
438528
}
439529

530+
void Spill2Reg::StackSlotDataEntry::MIDataWithLiveIn::dump() const {
531+
dbgs() << " (" << *MO << ") " << *MI << " IsLiveIn: " << IsLiveIn;
532+
}
533+
440534
void Spill2Reg::StackSlotDataEntry::dump() const {
441535
dbgs().indent(DumpInd) << "Disable: " << Disable << "\n";
442536
dbgs().indent(DumpInd) << "Spills:\n";

‎llvm/test/CodeGen/X86/spill2reg_liveins_reload_before_spill.mir‎

Lines changed: 74 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,74 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+
# RUN: llc %s -o - -mtriple=x86_64-unknown-linux -enable-spill2reg -mattr=+sse4.1 --run-pass=spill2reg -simplify-mir -spill2reg-mem-instrs=0 -spill2reg-vec-instrs=99999 | FileCheck %s
3+
4+
# Check that the liveins of a MBB get updated correctly if it contains a reload
5+
# before a spill.
6+
7+
# bb.0:
8+
# spill stack.0
9+
# JMP bb.1
10+
#
11+
# bb.1:
12+
# reload stack.0
13+
# spill stack.0
14+
# JMP bb.2
15+
#
16+
# bb.2:
17+
# reload stack.0
18+
19+
20+
--- |
21+
@D0 = dso_local local_unnamed_addr global i32 0, align 4
22+
@U0 = dso_local local_unnamed_addr global i32 0, align 4
23+
define void @func() { ret void }
24+
...
25+
---
26+
name: func
27+
alignment: 16
28+
tracksRegLiveness: true
29+
tracksDebugUserValues: true
30+
frameInfo:
31+
maxAlignment: 4
32+
stack:
33+
- { id: 0, type: spill-slot, size: 4, alignment: 4 }
34+
machineFunctionInfo: {}
35+
body: |
36+
; CHECK-LABEL: name: func
37+
; CHECK: bb.0:
38+
; CHECK-NEXT: $eax = MOV32rm $rip, 1, $noreg, @D0, $noreg :: (dereferenceable load (s32) from @D0)
39+
; CHECK-NEXT: $xmm0 = MOVDI2PDIrr $eax
40+
; CHECK-NEXT: JMP_1 %bb.1
41+
; CHECK-NEXT: {{ $}}
42+
; CHECK-NEXT: bb.1:
43+
; CHECK-NEXT: liveins: $xmm0
44+
; CHECK-NEXT: {{ $}}
45+
; CHECK-NEXT: $eax = MOVPDI2DIrr $xmm0
46+
; CHECK-NEXT: $xmm0 = MOVDI2PDIrr $eax
47+
; CHECK-NEXT: JMP_1 %bb.2
48+
; CHECK-NEXT: {{ $}}
49+
; CHECK-NEXT: bb.2:
50+
; CHECK-NEXT: liveins: $xmm0
51+
; CHECK-NEXT: {{ $}}
52+
; CHECK-NEXT: $eax = MOVPDI2DIrr $xmm0
53+
; CHECK-NEXT: RET 0
54+
55+
56+
57+
bb.0:
58+
$eax = MOV32rm $rip, 1, $noreg, @D0, $noreg :: (dereferenceable load (s32) from @D0)
59+
; Spill stack.0
60+
MOV32mr %stack.0, 1, $noreg, 0, $noreg, killed renamable $eax :: (store (s32) into %stack.0)
61+
JMP_1 %bb.1
62+
63+
bb.1:
64+
; Reload stack.0
65+
$eax = MOV32rm %stack.0, 1, $noreg, 0, $noreg :: (load (s32) from %stack.0)
66+
; Spill stack.0
67+
MOV32mr %stack.0, 1, $noreg, 0, $noreg, killed renamable $eax :: (store (s32) into %stack.0)
68+
JMP_1 %bb.2
69+
70+
bb.2:
71+
; Reload
72+
$eax = MOV32rm %stack.0, 1, $noreg, 0, $noreg :: (load (s32) from %stack.0)
73+
RET 0
74+
...

‎llvm/test/CodeGen/X86/spill2reg_liveins_spill_override.mir‎

Lines changed: 103 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,103 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+
# RUN: llc %s -o - -mtriple=x86_64-unknown-linux -enable-spill2reg -mattr=+sse4.1 --run-pass=spill2reg -simplify-mir -spill2reg-mem-instrs=0 -spill2reg-vec-instrs=99999 | FileCheck %s
3+
4+
5+
# Checks that spills that are overriden by other spills (like spill0 by spill1)
6+
# are not marked as live-in.
7+
# Also checks live reg tracking with spills-reload pairs separated by an instr
8+
# that clobbers the xmm registers.
9+
10+
# BB0:
11+
# [stack.0] = ... ; spill0
12+
# BB1:
13+
# [stack.0] = ... ; spill1
14+
# ... = [stack.0] ; reload1
15+
# call ; clobbers xmm regs
16+
# [stack.0] = ... ; spill2
17+
# ... = [stack.0] ; reload2
18+
# BB2:
19+
# ... = [stack.0] ; reload3
20+
21+
--- |
22+
@D0 = dso_local local_unnamed_addr global i32 0, align 4
23+
@U0 = dso_local local_unnamed_addr global i32 0, align 4
24+
declare void @foo()
25+
define void @func() { ret void }
26+
...
27+
---
28+
name: func
29+
alignment: 16
30+
tracksRegLiveness: true
31+
tracksDebugUserValues: true
32+
frameInfo:
33+
maxAlignment: 4
34+
stack:
35+
- { id: 0, type: spill-slot, size: 4, alignment: 4 }
36+
machineFunctionInfo: {}
37+
body: |
38+
; CHECK-LABEL: name: func
39+
; CHECK: bb.0:
40+
; CHECK-NEXT: $eax = MOV32rm $rip, 1, $noreg, @D0, $noreg :: (dereferenceable load (s32) from @D0)
41+
; CHECK-NEXT: $xmm0 = MOVDI2PDIrr $eax
42+
; CHECK-NEXT: {{ $}}
43+
; CHECK-NEXT: bb.1:
44+
; CHECK-NEXT: $eax = MOV32rm $rip, 1, $noreg, @D0, $noreg :: (dereferenceable load (s32) from @D0)
45+
; CHECK-NEXT: $xmm0 = MOVDI2PDIrr $eax
46+
; CHECK-NEXT: $eax = MOVPDI2DIrr $xmm0
47+
; CHECK-NEXT: MOV32mr $rip, 1, $noreg, @U0, $noreg, killed renamable $eax :: (store (s32) into @U0)
48+
; CHECK-NEXT: CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit-def $rsp
49+
; CHECK-NEXT: $eax = MOV32rm $rip, 1, $noreg, @D0, $noreg :: (dereferenceable load (s32) from @D0)
50+
; CHECK-NEXT: $xmm0 = MOVDI2PDIrr $eax
51+
; CHECK-NEXT: $eax = MOVPDI2DIrr $xmm0
52+
; CHECK-NEXT: MOV32mr $rip, 1, $noreg, @U0, $noreg, killed renamable $eax :: (store (s32) into @U0)
53+
; CHECK-NEXT: JMP_1 %bb.2
54+
; CHECK-NEXT: {{ $}}
55+
; CHECK-NEXT: bb.2:
56+
; CHECK-NEXT: liveins: $xmm0
57+
; CHECK-NEXT: {{ $}}
58+
; CHECK-NEXT: $eax = MOVPDI2DIrr $xmm0
59+
; CHECK-NEXT: MOV32mr $rip, 1, $noreg, @U0, $noreg, killed renamable $eax :: (store (s32) into @U0)
60+
; CHECK-NEXT: RET 0
61+
62+
63+
64+
bb.0:
65+
successors: %bb.1
66+
$eax = MOV32rm $rip, 1, $noreg, @D0, $noreg :: (dereferenceable load (s32) from @D0)
67+
; spill0
68+
MOV32mr %stack.0, 1, $noreg, 0, $noreg, killed renamable $eax :: (store (s32) into %stack.0)
69+
70+
bb.1:
71+
successors: %bb.2
72+
; spill1
73+
$eax = MOV32rm $rip, 1, $noreg, @D0, $noreg :: (dereferenceable load (s32) from @D0)
74+
MOV32mr %stack.0, 1, $noreg, 0, $noreg, killed renamable $eax :: (store (s32) into %stack.0)
75+
76+
; reload1
77+
$eax = MOV32rm %stack.0, 1, $noreg, 0, $noreg :: (load (s32) from %stack.0)
78+
MOV32mr $rip, 1, $noreg, @U0, $noreg, killed renamable $eax :: (store (s32) into @U0)
79+
80+
; The call clobbers all xmm regs
81+
CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit-def $rsp
82+
83+
; spill2
84+
$eax = MOV32rm $rip, 1, $noreg, @D0, $noreg :: (dereferenceable load (s32) from @D0)
85+
MOV32mr %stack.0, 1, $noreg, 0, $noreg, killed renamable $eax :: (store (s32) into %stack.0)
86+
87+
; reload2
88+
$eax = MOV32rm %stack.0, 1, $noreg, 0, $noreg :: (load (s32) from %stack.0)
89+
MOV32mr $rip, 1, $noreg, @U0, $noreg, killed renamable $eax :: (store (s32) into @U0)
90+
JMP_1 %bb.2
91+
92+
bb.2:
93+
; reload3
94+
$eax = MOV32rm %stack.0, 1, $noreg, 0, $noreg :: (load (s32) from %stack.0)
95+
MOV32mr $rip, 1, $noreg, @U0, $noreg, killed renamable $eax :: (store (s32) into @U0)
96+
RET 0
97+
...
98+
99+
100+
101+
102+
103+

‎llvm/test/CodeGen/X86/spill2reg_liveregs_bbs.mir‎

Lines changed: 73 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,73 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+
# RUN: llc %s -o - -mtriple=x86_64-unknown-linux -enable-spill2reg -mattr=+sse4.1 --run-pass=spill2reg -simplify-mir -spill2reg-mem-instrs=0 -spill2reg-vec-instrs=99999 | FileCheck %s
3+
4+
# Check that live reg tracking works correctly when one live range spans
5+
# multiple blocks and the other spans a single block.
6+
# BB0:
7+
# [stack.0] = ...
8+
# BB1:
9+
# [stack.1] = ...
10+
# ... = [stack.1]
11+
# BB2:
12+
# ... = [stack.0]
13+
14+
--- |
15+
@D0 = dso_local local_unnamed_addr global i32 0, align 4
16+
@D1 = dso_local local_unnamed_addr global i32 0, align 4
17+
@U0 = dso_local local_unnamed_addr global i32 0, align 4
18+
@U1 = dso_local local_unnamed_addr global i32 0, align 4
19+
define void @func() { ret void }
20+
...
21+
---
22+
name: func
23+
alignment: 16
24+
tracksRegLiveness: true
25+
tracksDebugUserValues: true
26+
frameInfo:
27+
maxAlignment: 4
28+
stack:
29+
- { id: 0, type: spill-slot, size: 4, alignment: 4 }
30+
- { id: 1, type: spill-slot, size: 4, alignment: 4 }
31+
machineFunctionInfo: {}
32+
body: |
33+
; CHECK-LABEL: name: func
34+
; CHECK: bb.0:
35+
; CHECK-NEXT: $eax = MOV32rm $rip, 1, $noreg, @D0, $noreg :: (dereferenceable load (s32) from @D0)
36+
; CHECK-NEXT: $xmm0 = MOVDI2PDIrr $eax
37+
; CHECK-NEXT: {{ $}}
38+
; CHECK-NEXT: bb.1:
39+
; CHECK-NEXT: liveins: $xmm0
40+
; CHECK-NEXT: {{ $}}
41+
; CHECK-NEXT: $eax = MOV32rm $rip, 1, $noreg, @D1, $noreg :: (dereferenceable load (s32) from @D1)
42+
; CHECK-NEXT: $xmm1 = MOVDI2PDIrr $eax
43+
; CHECK-NEXT: $eax = MOVPDI2DIrr $xmm1
44+
; CHECK-NEXT: MOV32mr $rip, 1, $noreg, @U1, $noreg, killed renamable $eax :: (store (s32) into @U1)
45+
; CHECK-NEXT: JMP_1 %bb.2
46+
; CHECK-NEXT: {{ $}}
47+
; CHECK-NEXT: bb.2:
48+
; CHECK-NEXT: liveins: $xmm0
49+
; CHECK-NEXT: {{ $}}
50+
; CHECK-NEXT: $eax = MOVPDI2DIrr $xmm0
51+
; CHECK-NEXT: MOV32mr $rip, 1, $noreg, @U0, $noreg, killed renamable $eax :: (store (s32) into @U0)
52+
; CHECK-NEXT: RET 0
53+
54+
55+
56+
bb.0:
57+
successors: %bb.1
58+
$eax = MOV32rm $rip, 1, $noreg, @D0, $noreg :: (dereferenceable load (s32) from @D0)
59+
MOV32mr %stack.0, 1, $noreg, 0, $noreg, killed renamable $eax :: (store (s32) into %stack.0)
60+
61+
bb.1:
62+
successors: %bb.2
63+
$eax = MOV32rm $rip, 1, $noreg, @D1, $noreg :: (dereferenceable load (s32) from @D1)
64+
MOV32mr %stack.1, 1, $noreg, 0, $noreg, killed renamable $eax :: (store (s32) into %stack.1)
65+
$eax = MOV32rm %stack.1, 1, $noreg, 0, $noreg :: (load (s32) from %stack.1)
66+
MOV32mr $rip, 1, $noreg, @U1, $noreg, killed renamable $eax :: (store (s32) into @U1)
67+
JMP_1 %bb.2
68+
69+
bb.2:
70+
$eax = MOV32rm %stack.0, 1, $noreg, 0, $noreg :: (load (s32) from %stack.0)
71+
MOV32mr $rip, 1, $noreg, @U0, $noreg, killed renamable $eax :: (store (s32) into @U0)
72+
RET 0
73+
...

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