Make instruction param const.

Change-Id: Iede7601d616f29dff3e04182d94e9a5f233ccf66

Author: UsmanNadeem

llvm/include/llvm/CodeGen/TargetLowering.h

@@ -2245,7 +2245,7 @@ class LLVM_ABI TargetLoweringBase {
 
   /// Whether AtomicExpandPass should automatically insert a trailing fence
   /// without reducing the ordering for this atomic. Defaults to false.
-  virtual bool storeNeedsSeqCstTrailingFence(Instruction *I) const {
+  virtual bool storeNeedsSeqCstTrailingFence(const Instruction *I) const {
     return false;
   }
 

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

@@ -29447,7 +29447,7 @@ bool AArch64TargetLowering::shouldInsertFencesForAtomic(
 }
 
 bool AArch64TargetLowering::storeNeedsSeqCstTrailingFence(
-    Instruction *I) const {
+    const Instruction *I) const {
   // Store-Release instructions only provide seq_cst guarantees when paired with
   // Load-Acquire instructions. MSVC CRT does not use these instructions to
   // implement seq_cst loads and stores, so we need additional explicit fences

llvm/lib/Target/AArch64/AArch64ISelLowering.h

@@ -349,7 +349,7 @@ class AArch64TargetLowering : public TargetLowering {
   bool isOpSuitableForLSE128(const Instruction *I) const;
   bool isOpSuitableForRCPC3(const Instruction *I) const;
   bool shouldInsertFencesForAtomic(const Instruction *I) const override;
-  bool storeNeedsSeqCstTrailingFence(Instruction *I) const override;
+  bool storeNeedsSeqCstTrailingFence(const Instruction *I) const override;
 
   TargetLoweringBase::AtomicExpansionKind
   shouldExpandAtomicLoadInIR(LoadInst *LI) const override;