[RISCV][CostModel] Test default lowering strategy for vector LD/ST

Summary:
Remove two options from the test command line:

* -riscv-v-vector-bits-min=128 -- This has no effect as v implied zvl128b,
  which provides the same minimum.
* -riscv-v-fixed-length-vector-lmul-max=1 -- This one forced the backend
  to split as if LMUL>m1 were illegal.  This diverges significantly from
  default behavior (where all LMUL are legal).  Note that we do still
  have splitting test coverage after this change.  Look at e.g. 32 x i64.

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Differential Revision: https://phabricator.intern.facebook.com/D60250610

Author: preames