Revert "Check for loops"

This reverts commit a703c3b.

Author: mikhailramalho

llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

@@ -943,10 +943,8 @@ RISCVInsertVSETVLI::getInfoForVSETVLI(const MachineInstr &MI) const {
     NewInfo.setAVLImm(MI.getOperand(1).getImm());
   } else {
     assert(MI.getOpcode() == RISCV::PseudoVSETVLI ||
-           MI.getOpcode() == RISCV::PseudoVSETVLIX0 ||
-           MI.getOpcode() == RISCV::PseudoVSETVLIX0X0);
-    if (MI.getOpcode() == RISCV::PseudoVSETVLIX0 ||
-        MI.getOpcode() == RISCV::PseudoVSETVLIX0X0)
+           MI.getOpcode() == RISCV::PseudoVSETVLIX0);
+    if (MI.getOpcode() == RISCV::PseudoVSETVLIX0)
       NewInfo.setAVLVLMAX();
     else if (MI.getOperand(1).isUndef())
       // Otherwise use an AVL of 1 to avoid depending on previous vl.
@@ -1513,21 +1511,12 @@ void RISCVInsertVSETVLI::emitVSETVLIs(MachineBasicBlock &MBB) {
 /// this is geared to catch the common case of a fixed length vsetvl in a single
 /// block loop when it could execute once in the preheader instead.
 void RISCVInsertVSETVLI::doPRE(MachineBasicBlock &MBB) {
-  // Only works for either one predecessor, or two predecessors if it's a loop
-  if (MBB.pred_empty() && MBB.pred_size() > 2)
-    return;
-
   if (!BlockInfo[MBB.getNumber()].Pred.isUnknown())
     return;
 
-  bool isLoop = false;
-
   MachineBasicBlock *UnavailablePred = nullptr;
   VSETVLIInfo AvailableInfo;
-  MachineBasicBlock *PreviousPred = nullptr;
   for (MachineBasicBlock *P : MBB.predecessors()) {
-    isLoop |= (P == &MBB);
-
     const VSETVLIInfo &PredInfo = BlockInfo[P->getNumber()].Exit;
     if (PredInfo.isUnknown()) {
       if (UnavailablePred)
@@ -1536,24 +1525,8 @@ void RISCVInsertVSETVLI::doPRE(MachineBasicBlock &MBB) {
     } else if (!AvailableInfo.isValid()) {
       AvailableInfo = PredInfo;
     } else if (AvailableInfo != PredInfo) {
-      if (!isLoop)
-        return;
-
-      DemandedFields PREDemands;
-      PREDemands.demandVTYPE();
-
-      if (!PredInfo.isCompatible(PREDemands, AvailableInfo, LIS))
-        return;
-
-      // States are VTYPE-compatible, prefer the more general state
-      // Choose VLMAX over immediate when both are tail-agnostic
-      if (PredInfo.hasAVLVLMAX() && AvailableInfo.hasAVLImm()) {
-        AvailableInfo = PredInfo;
-        UnavailablePred = PreviousPred;
-      }
+      return;
     }
-
-    PreviousPred = P;
   }
 
   // Unreachable, single pred, or full redundancy. Note that FRE is handled by
@@ -1570,7 +1543,7 @@ void RISCVInsertVSETVLI::doPRE(MachineBasicBlock &MBB) {
     return;
 
   // Critical edge - TODO: consider splitting?
-  if (UnavailablePred->succ_size() != 1 && !isLoop)
+  if (UnavailablePred->succ_size() != 1)
     return;
 
   // If the AVL value is a register (other than our VLMAX sentinel),
@@ -1598,49 +1571,21 @@ void RISCVInsertVSETVLI::doPRE(MachineBasicBlock &MBB) {
   VSETVLIInfo OldInfo = BlockInfo[MBB.getNumber()].Pred;
   VSETVLIInfo CurInfo = AvailableInfo;
   int TransitionsRemoved = 0;
-
-  LLVM_DEBUG(dbgs() << "PRE VSETVLI from " << MBB.getName() << " to "
-                    << UnavailablePred->getName() << "\n"
-                    << "  Old state: " << OldInfo << "\n"
-                    << "  New state: " << CurInfo << "\n");
-
   for (const MachineInstr &MI : MBB) {
-    if (RISCVII::hasSEWOp(MI.getDesc().TSFlags))
-      if (!hasUndefinedPassthru(MI))
-        return; // Unsafe to change VL/VTYPE for this loop.
-
     const VSETVLIInfo LastInfo = CurInfo;
     const VSETVLIInfo LastOldInfo = OldInfo;
     transferBefore(CurInfo, MI);
     transferBefore(OldInfo, MI);
-
-    LLVM_DEBUG(dbgs() << "PRE VSETVLI 1 from " << MBB.getName() << " to "
-                      << UnavailablePred->getName() << "\n"
-                      << "  Old state: " << OldInfo << "\n"
-                      << "  New state: " << CurInfo << "\n");
-
     if (CurInfo == LastInfo)
       TransitionsRemoved++;
     if (LastOldInfo == OldInfo)
       TransitionsRemoved--;
     transferAfter(CurInfo, MI);
     transferAfter(OldInfo, MI);
-
-    LLVM_DEBUG(dbgs() << "PRE VSETVLI 2 from " << MBB.getName() << " to "
-                      << UnavailablePred->getName() << "\n"
-                      << "  Old state: " << OldInfo << "\n"
-                      << "  New state: " << CurInfo << "\n\n");
-
     if (CurInfo == OldInfo)
       // Convergence.  All transitions after this must match by construction.
       break;
   }
-
-  LLVM_DEBUG(dbgs() << "PRE VSETVLI 3 from " << MBB.getName() << " to "
-                  << UnavailablePred->getName() << "\n"
-                  << "  Old state: " << OldInfo << "\n"
-                  << "  New state: " << CurInfo << "\n");
-
   if (CurInfo != OldInfo || TransitionsRemoved <= 0)
     // Issues 1 and 2 above
     return;

llvm/test/CodeGen/AArch64/misched-cutoff.mir

@@ -42,8 +42,8 @@ body: |
     ; CHECK-CUTOFF: liveins: $w1, $x0
     ; CHECK-CUTOFF-NEXT: {{  $}}
     ; CHECK-CUTOFF-NEXT: $w8 = LDRWui $x0, 1, implicit-def $x8 :: (load (s32) from %ir.0)
-    ; CHECK-CUTOFF-NEXT: $w9 = LDRWui $x0, 0, implicit-def $x9 :: (load (s32) from %ir.arrayidx19, align 8)
     ; CHECK-CUTOFF-NEXT: STRWui $w1, $x0, 2 :: (store (s32) into %ir.arrayidx1)
+    ; CHECK-CUTOFF-NEXT: $w9 = LDRWui $x0, 0, implicit-def $x9 :: (load (s32) from %ir.arrayidx19, align 8)
     ; CHECK-CUTOFF-NEXT: $x0 = ADDXrr killed $x9, killed $x8
     ; CHECK-CUTOFF-NEXT: RET_ReallyLR implicit $x0
     $w8 = LDRWui $x0, 1, implicit-def $x8  :: (load (s32) from %ir.0)

llvm/test/CodeGen/RISCV/machinelicm-constant-phys-reg.ll

@@ -7,13 +7,14 @@ define i32 @test(ptr %a, i64 %n)  {
 ; CHECK-LABEL: test:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    li a3, 0
-; CHECK-NEXT:    vsetvli a2, zero, e32, m1, ta, ma
+; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
 ; CHECK-NEXT:    vmv.s.x v8, zero
 ; CHECK-NEXT:  .LBB0_1: # %loop
 ; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    vl1re32.v v9, (a0)
 ; CHECK-NEXT:    mv a2, a3
 ; CHECK-NEXT:    addi a1, a1, -1
+; CHECK-NEXT:    vsetvli a3, zero, e32, m1, ta, ma
 ; CHECK-NEXT:    vredsum.vs v9, v9, v8
 ; CHECK-NEXT:    vmv.x.s a3, v9
 ; CHECK-NEXT:    addw a3, a3, a3

llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll

@@ -2087,13 +2087,13 @@ define void @sink_splat_fma_scalable(ptr noalias nocapture %a, ptr noalias nocap
 ; CHECK-NEXT:    mv a6, a0
 ; CHECK-NEXT:    mv a7, a1
 ; CHECK-NEXT:    mv t0, a3
+; CHECK-NEXT:    vsetvli t1, zero, e32, m1, ta, ma
 ; CHECK-NEXT:  .LBB34_3: # %vector.body
 ; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    vl1re32.v v8, (a6)
 ; CHECK-NEXT:    vl1re32.v v9, (a7)
 ; CHECK-NEXT:    sub t0, t0, a4
 ; CHECK-NEXT:    add a7, a7, a2
-; CHECK-NEXT:    vsetvli t1, zero, e32, m1, ta, ma
 ; CHECK-NEXT:    vfmacc.vf v9, fa0, v8
 ; CHECK-NEXT:    vs1r.v v9, (a6)
 ; CHECK-NEXT:    add a6, a6, a2
@@ -2187,13 +2187,13 @@ define void @sink_splat_fma_commute_scalable(ptr noalias nocapture %a, ptr noali
 ; CHECK-NEXT:    mv a6, a0
 ; CHECK-NEXT:    mv a7, a1
 ; CHECK-NEXT:    mv t0, a3
+; CHECK-NEXT:    vsetvli t1, zero, e32, m1, ta, ma
 ; CHECK-NEXT:  .LBB35_3: # %vector.body
 ; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    vl1re32.v v8, (a6)
 ; CHECK-NEXT:    vl1re32.v v9, (a7)
 ; CHECK-NEXT:    sub t0, t0, a4
 ; CHECK-NEXT:    add a7, a7, a2
-; CHECK-NEXT:    vsetvli t1, zero, e32, m1, ta, ma
 ; CHECK-NEXT:    vfmacc.vf v9, fa0, v8
 ; CHECK-NEXT:    vs1r.v v9, (a6)
 ; CHECK-NEXT:    add a6, a6, a2