use RISCVSubtarget

Author: svs-quic

llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp

@@ -789,8 +789,7 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
     RISCVCC::CondCode CC;
     getOperandsForBranch(MI.getOperand(0).getReg(), CC, LHS, RHS, *MRI);
 
-    auto Bcc = MIB.buildInstr(RISCVCC::getBrCond(CC, STI.getFeatureBits()), {},
-                              {LHS, RHS})
+    auto Bcc = MIB.buildInstr(RISCVCC::getBrCond(STI, CC), {}, {LHS, RHS})
                    .addMBB(MI.getOperand(1).getMBB());
     MI.eraseFromParent();
     return constrainSelectedInstRegOperands(*Bcc, TII, TRI, RBI);

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

@@ -953,21 +953,21 @@ static void parseCondBranch(MachineInstr &LastInst, MachineBasicBlock *&Target,
   Cond.push_back(LastInst.getOperand(1));
 }
 
-unsigned RISCVCC::getBrCond(RISCVCC::CondCode CC,
-                            const FeatureBitset &FeatureBits, bool Imm) {
+unsigned RISCVCC::getBrCond(const RISCVSubtarget &STI, RISCVCC::CondCode CC,
+                            bool Imm) {
   switch (CC) {
   default:
     llvm_unreachable("Unknown condition code!");
   case RISCVCC::COND_EQ:
     if (!Imm)
       return RISCV::BEQ;
-    if (FeatureBits[RISCV::FeatureVendorXCVbi])
+    if (STI.hasVendorXCVbi())
       return RISCV::CV_BEQIMM;
     llvm_unreachable("Unknown branch immediate!");
   case RISCVCC::COND_NE:
     if (!Imm)
       return RISCV::BNE;
-    if (FeatureBits[RISCV::FeatureVendorXCVbi])
+    if (STI.hasVendorXCVbi())
       return RISCV::CV_BNEIMM;
     llvm_unreachable("Unknown branch immediate!");
   case RISCVCC::COND_LT:
@@ -983,7 +983,7 @@ unsigned RISCVCC::getBrCond(RISCVCC::CondCode CC,
 
 const MCInstrDesc &RISCVInstrInfo::getBrCond(RISCVCC::CondCode CC,
                                              bool Imm) const {
-  return get(RISCVCC::getBrCond(CC, STI.getFeatureBits(), Imm));
+  return get(RISCVCC::getBrCond(STI, CC, Imm));
 }
 
 RISCVCC::CondCode RISCVCC::getOppositeBranchCondition(RISCVCC::CondCode CC) {

llvm/lib/Target/RISCV/RISCVInstrInfo.h

@@ -45,8 +45,7 @@ enum CondCode {
 };
 
 CondCode getOppositeBranchCondition(CondCode);
-unsigned getBrCond(CondCode CC, const FeatureBitset &FeatureBits,
-                   bool Imm = false);
+unsigned getBrCond(const RISCVSubtarget &STI, CondCode CC, bool Imm = false);
 
 } // end of namespace RISCVCC