[NVPTX] expand vector_shuffle, insertelt for v2f32 and lower i64 bitcast

Fixes test/CodeGen/Generic/vector.ll

Author: Prince781

llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp

@@ -621,6 +621,8 @@ NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
   setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i8, Custom);
 
   setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f32, Custom);
+  setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f32, Expand);
+  setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f32, Expand);
 
   // Custom conversions to/from v2i8.
   setOperationAction(ISD::BITCAST, MVT::v2i8, Custom);

llvm/lib/Target/NVPTX/NVPTXInstrInfo.td

@@ -2712,6 +2712,9 @@ foreach ta = [v2f16, v2bf16, v2i16, v4i8, i32] in {
   }
 }
 
+def: Pat<(i64 (bitconvert v2f32:$a)),
+         (i64 Int64Regs:$a)>;
+
 // NOTE: pred->fp are currently sub-optimal due to an issue in TableGen where
 // we cannot specify floating-point literals in isel patterns.  Therefore, we
 // use an integer selp to select either 1 (or -1 in case of signed) or 0