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1 parent ea480cc commit f7291c2Copy full SHA for f7291c2
llvm/test/CodeGen/RISCV/rvv/fp4-bitcast.ll
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+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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+; RUN: llc -mtriple=riscv64 -mattr='+v' < %s | FileCheck %s
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+
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+define <2 x i8> @fp4(<4 x i4> %0) nounwind {
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+; CHECK-LABEL: fp4:
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+; CHECK: # %bb.0:
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+; CHECK-NEXT: ret
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+ %2 = bitcast <4 x i4> %0 to <2 x i8>
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+ ret <2 x i8> %2
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+}
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