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| 1 | +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 |
1 | 2 | ; RUN: opt < %s -passes=gvn -S | FileCheck %s
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2 |
| -; |
3 | 3 |
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4 | 4 | %0 = type { i64, i1 }
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5 | 5 |
|
6 | 6 | define i64 @test1(i64 %a, i64 %b) nounwind ssp {
|
| 7 | +; CHECK-LABEL: define i64 @test1( |
| 8 | +; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0:[0-9]+]] { |
| 9 | +; CHECK-NEXT: [[ENTRY:.*:]] |
| 10 | +; CHECK-NEXT: [[TMP0:%.*]] = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 [[A]], i64 [[B]]) |
| 11 | +; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { i64, i1 } [[TMP0]], 0 |
| 12 | +; CHECK-NEXT: [[TMP2:%.*]] = insertvalue [[TMP0]] poison, i64 [[TMP1]], 0 |
| 13 | +; CHECK-NEXT: [[TMP3:%.*]] = extractvalue { i64, i1 } [[TMP0]], 1 |
| 14 | +; CHECK-NEXT: [[TMP4:%.*]] = insertvalue [[TMP0]] [[TMP2]], i1 [[TMP3]], 1 |
| 15 | +; CHECK-NEXT: ret i64 [[TMP1]] |
| 16 | +; |
7 | 17 | entry:
|
8 | 18 | %uadd = tail call %0 @llvm.uadd.with.overflow.i64(i64 %a, i64 %b)
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9 | 19 | %uadd.0 = extractvalue %0 %uadd, 0
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10 | 20 | %add1 = add i64 %a, %b
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11 | 21 | ret i64 %add1
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12 | 22 | }
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13 | 23 |
|
14 |
| -; CHECK-LABEL: @test1( |
15 |
| -; CHECK-NOT: add1 |
16 |
| -; CHECK: ret |
17 |
| - |
18 | 24 | define i64 @test2(i64 %a, i64 %b) nounwind ssp {
|
| 25 | +; CHECK-LABEL: define i64 @test2( |
| 26 | +; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { |
| 27 | +; CHECK-NEXT: [[ENTRY:.*:]] |
| 28 | +; CHECK-NEXT: [[TMP0:%.*]] = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 [[A]], i64 [[B]]) |
| 29 | +; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { i64, i1 } [[TMP0]], 0 |
| 30 | +; CHECK-NEXT: [[TMP2:%.*]] = insertvalue [[TMP0]] poison, i64 [[TMP1]], 0 |
| 31 | +; CHECK-NEXT: [[TMP3:%.*]] = extractvalue { i64, i1 } [[TMP0]], 1 |
| 32 | +; CHECK-NEXT: [[TMP4:%.*]] = insertvalue [[TMP0]] [[TMP2]], i1 [[TMP3]], 1 |
| 33 | +; CHECK-NEXT: ret i64 [[TMP1]] |
| 34 | +; |
19 | 35 | entry:
|
20 | 36 | %usub = tail call %0 @llvm.usub.with.overflow.i64(i64 %a, i64 %b)
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21 | 37 | %usub.0 = extractvalue %0 %usub, 0
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22 | 38 | %sub1 = sub i64 %a, %b
|
23 | 39 | ret i64 %sub1
|
24 | 40 | }
|
25 | 41 |
|
26 |
| -; CHECK-LABEL: @test2( |
27 |
| -; CHECK-NOT: sub1 |
28 |
| -; CHECK: ret |
29 |
| - |
30 | 42 | define i64 @test3(i64 %a, i64 %b) nounwind ssp {
|
| 43 | +; CHECK-LABEL: define i64 @test3( |
| 44 | +; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { |
| 45 | +; CHECK-NEXT: [[ENTRY:.*:]] |
| 46 | +; CHECK-NEXT: [[TMP0:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 [[A]], i64 [[B]]) |
| 47 | +; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { i64, i1 } [[TMP0]], 0 |
| 48 | +; CHECK-NEXT: [[TMP2:%.*]] = insertvalue [[TMP0]] poison, i64 [[TMP1]], 0 |
| 49 | +; CHECK-NEXT: [[TMP3:%.*]] = extractvalue { i64, i1 } [[TMP0]], 1 |
| 50 | +; CHECK-NEXT: [[TMP4:%.*]] = insertvalue [[TMP0]] [[TMP2]], i1 [[TMP3]], 1 |
| 51 | +; CHECK-NEXT: ret i64 [[TMP1]] |
| 52 | +; |
31 | 53 | entry:
|
32 | 54 | %umul = tail call %0 @llvm.umul.with.overflow.i64(i64 %a, i64 %b)
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33 | 55 | %umul.0 = extractvalue %0 %umul, 0
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34 | 56 | %mul1 = mul i64 %a, %b
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35 | 57 | ret i64 %mul1
|
36 | 58 | }
|
37 | 59 |
|
38 |
| -; CHECK-LABEL: @test3( |
39 |
| -; CHECK-NOT: mul1 |
40 |
| -; CHECK: ret |
41 |
| - |
42 | 60 | define i64 @test4(i64 %a, i64 %b) nounwind ssp {
|
| 61 | +; CHECK-LABEL: define i64 @test4( |
| 62 | +; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { |
| 63 | +; CHECK-NEXT: [[ENTRY:.*:]] |
| 64 | +; CHECK-NEXT: [[TMP0:%.*]] = call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 [[A]], i64 [[B]]) |
| 65 | +; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { i64, i1 } [[TMP0]], 0 |
| 66 | +; CHECK-NEXT: [[TMP2:%.*]] = insertvalue [[TMP0]] poison, i64 [[TMP1]], 0 |
| 67 | +; CHECK-NEXT: [[TMP3:%.*]] = extractvalue { i64, i1 } [[TMP0]], 1 |
| 68 | +; CHECK-NEXT: [[TMP4:%.*]] = insertvalue [[TMP0]] [[TMP2]], i1 [[TMP3]], 1 |
| 69 | +; CHECK-NEXT: ret i64 [[TMP1]] |
| 70 | +; |
43 | 71 | entry:
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44 | 72 | %sadd = tail call %0 @llvm.sadd.with.overflow.i64(i64 %a, i64 %b)
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45 | 73 | %sadd.0 = extractvalue %0 %sadd, 0
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46 | 74 | %add1 = add i64 %a, %b
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47 | 75 | ret i64 %add1
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48 | 76 | }
|
49 | 77 |
|
50 |
| -; CHECK-LABEL: @test4( |
51 |
| -; CHECK-NOT: add1 |
52 |
| -; CHECK: ret |
53 |
| - |
54 | 78 | define i64 @test5(i64 %a, i64 %b) nounwind ssp {
|
| 79 | +; CHECK-LABEL: define i64 @test5( |
| 80 | +; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { |
| 81 | +; CHECK-NEXT: [[ENTRY:.*:]] |
| 82 | +; CHECK-NEXT: [[TMP0:%.*]] = call { i64, i1 } @llvm.ssub.with.overflow.i64(i64 [[A]], i64 [[B]]) |
| 83 | +; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { i64, i1 } [[TMP0]], 0 |
| 84 | +; CHECK-NEXT: [[TMP2:%.*]] = insertvalue [[TMP0]] poison, i64 [[TMP1]], 0 |
| 85 | +; CHECK-NEXT: [[TMP3:%.*]] = extractvalue { i64, i1 } [[TMP0]], 1 |
| 86 | +; CHECK-NEXT: [[TMP4:%.*]] = insertvalue [[TMP0]] [[TMP2]], i1 [[TMP3]], 1 |
| 87 | +; CHECK-NEXT: ret i64 [[TMP1]] |
| 88 | +; |
55 | 89 | entry:
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56 | 90 | %ssub = tail call %0 @llvm.ssub.with.overflow.i64(i64 %a, i64 %b)
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57 | 91 | %ssub.0 = extractvalue %0 %ssub, 0
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58 | 92 | %sub1 = sub i64 %a, %b
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59 | 93 | ret i64 %sub1
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60 | 94 | }
|
61 | 95 |
|
62 |
| -; CHECK-LABEL: @test5( |
63 |
| -; CHECK-NOT: sub1 |
64 |
| -; CHECK: ret |
65 |
| - |
66 | 96 | define i64 @test6(i64 %a, i64 %b) nounwind ssp {
|
| 97 | +; CHECK-LABEL: define i64 @test6( |
| 98 | +; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { |
| 99 | +; CHECK-NEXT: [[ENTRY:.*:]] |
| 100 | +; CHECK-NEXT: [[TMP0:%.*]] = call { i64, i1 } @llvm.smul.with.overflow.i64(i64 [[A]], i64 [[B]]) |
| 101 | +; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { i64, i1 } [[TMP0]], 0 |
| 102 | +; CHECK-NEXT: [[TMP2:%.*]] = insertvalue [[TMP0]] poison, i64 [[TMP1]], 0 |
| 103 | +; CHECK-NEXT: [[TMP3:%.*]] = extractvalue { i64, i1 } [[TMP0]], 1 |
| 104 | +; CHECK-NEXT: [[TMP4:%.*]] = insertvalue [[TMP0]] [[TMP2]], i1 [[TMP3]], 1 |
| 105 | +; CHECK-NEXT: ret i64 [[TMP1]] |
| 106 | +; |
67 | 107 | entry:
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68 | 108 | %smul = tail call %0 @llvm.smul.with.overflow.i64(i64 %a, i64 %b)
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69 | 109 | %smul.0 = extractvalue %0 %smul, 0
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70 | 110 | %mul1 = mul i64 %a, %b
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71 | 111 | ret i64 %mul1
|
72 | 112 | }
|
73 | 113 |
|
74 |
| -; CHECK-LABEL: @test6( |
75 |
| -; CHECK-NOT: mul1 |
76 |
| -; CHECK: ret |
77 |
| - |
78 | 114 | declare void @exit(i32) noreturn
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79 | 115 | declare %0 @llvm.uadd.with.overflow.i64(i64, i64) nounwind readnone
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80 | 116 | declare %0 @llvm.usub.with.overflow.i64(i64, i64) nounwind readnone
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81 | 117 | declare %0 @llvm.umul.with.overflow.i64(i64, i64) nounwind readnone
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82 | 118 | declare %0 @llvm.sadd.with.overflow.i64(i64, i64) nounwind readnone
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83 | 119 | declare %0 @llvm.ssub.with.overflow.i64(i64, i64) nounwind readnone
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84 | 120 | declare %0 @llvm.smul.with.overflow.i64(i64, i64) nounwind readnone
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85 |
| - |
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