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‎llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.inreg.1024bit.ll‎

Lines changed: 251 additions & 252 deletions
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‎llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.inreg.128bit.ll‎

Lines changed: 280 additions & 280 deletions
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‎llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.inreg.160bit.ll‎

Lines changed: 60 additions & 60 deletions
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‎llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.inreg.16bit.ll‎

Lines changed: 30 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -5,8 +5,8 @@
55
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
66
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11 %s
77

8-
define inreg half @s_bitcast_i16_to_f16_inreg(i16 inreg %a, i32 inreg %b) {
9-
; SI-LABEL: s_bitcast_i16_to_f16_inreg:
8+
define inreg half @s_bitcast_i16_to_f16(i16 inreg %a, i32 inreg %b) {
9+
; SI-LABEL: s_bitcast_i16_to_f16:
1010
; SI: ; %bb.0:
1111
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1212
; SI-NEXT: s_and_b32 s6, s16, 0xffff
@@ -24,7 +24,7 @@ define inreg half @s_bitcast_i16_to_f16_inreg(i16 inreg %a, i32 inreg %b) {
2424
; SI-NEXT: ; implicit-def: $vgpr0
2525
; SI-NEXT: s_branch .LBB0_2
2626
;
27-
; VI-LABEL: s_bitcast_i16_to_f16_inreg:
27+
; VI-LABEL: s_bitcast_i16_to_f16:
2828
; VI: ; %bb.0:
2929
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3030
; VI-NEXT: s_cmp_lg_u32 s17, 0
@@ -39,7 +39,7 @@ define inreg half @s_bitcast_i16_to_f16_inreg(i16 inreg %a, i32 inreg %b) {
3939
; VI-NEXT: .LBB0_4:
4040
; VI-NEXT: s_branch .LBB0_2
4141
;
42-
; GFX9-LABEL: s_bitcast_i16_to_f16_inreg:
42+
; GFX9-LABEL: s_bitcast_i16_to_f16:
4343
; GFX9: ; %bb.0:
4444
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4545
; GFX9-NEXT: s_cmp_lg_u32 s17, 0
@@ -54,7 +54,7 @@ define inreg half @s_bitcast_i16_to_f16_inreg(i16 inreg %a, i32 inreg %b) {
5454
; GFX9-NEXT: .LBB0_4:
5555
; GFX9-NEXT: s_branch .LBB0_2
5656
;
57-
; GFX11-LABEL: s_bitcast_i16_to_f16_inreg:
57+
; GFX11-LABEL: s_bitcast_i16_to_f16:
5858
; GFX11: ; %bb.0:
5959
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
6060
; GFX11-NEXT: s_cmp_lg_u32 s1, 0
@@ -89,8 +89,8 @@ end:
8989
ret half %phi
9090
}
9191

92-
define inreg i16 @s_bitcast_f16_to_i16_inreg(half inreg %a, i32 inreg %b) {
93-
; SI-LABEL: s_bitcast_f16_to_i16_inreg:
92+
define inreg i16 @s_bitcast_f16_to_i16(half inreg %a, i32 inreg %b) {
93+
; SI-LABEL: s_bitcast_f16_to_i16:
9494
; SI: ; %bb.0:
9595
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
9696
; SI-NEXT: v_cvt_f16_f32_e32 v0, s16
@@ -107,7 +107,7 @@ define inreg i16 @s_bitcast_f16_to_i16_inreg(half inreg %a, i32 inreg %b) {
107107
; SI-NEXT: .LBB1_4:
108108
; SI-NEXT: s_branch .LBB1_2
109109
;
110-
; VI-LABEL: s_bitcast_f16_to_i16_inreg:
110+
; VI-LABEL: s_bitcast_f16_to_i16:
111111
; VI: ; %bb.0:
112112
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
113113
; VI-NEXT: s_cmp_lg_u32 s17, 0
@@ -124,7 +124,7 @@ define inreg i16 @s_bitcast_f16_to_i16_inreg(half inreg %a, i32 inreg %b) {
124124
; VI-NEXT: v_mov_b32_e32 v0, s16
125125
; VI-NEXT: s_setpc_b64 s[30:31]
126126
;
127-
; GFX9-LABEL: s_bitcast_f16_to_i16_inreg:
127+
; GFX9-LABEL: s_bitcast_f16_to_i16:
128128
; GFX9: ; %bb.0:
129129
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
130130
; GFX9-NEXT: s_cmp_lg_u32 s17, 0
@@ -141,7 +141,7 @@ define inreg i16 @s_bitcast_f16_to_i16_inreg(half inreg %a, i32 inreg %b) {
141141
; GFX9-NEXT: v_mov_b32_e32 v0, s16
142142
; GFX9-NEXT: s_setpc_b64 s[30:31]
143143
;
144-
; GFX11-LABEL: s_bitcast_f16_to_i16_inreg:
144+
; GFX11-LABEL: s_bitcast_f16_to_i16:
145145
; GFX11: ; %bb.0:
146146
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
147147
; GFX11-NEXT: s_cmp_lg_u32 s1, 0
@@ -175,8 +175,8 @@ end:
175175
ret i16 %phi
176176
}
177177

178-
define inreg bfloat @s_bitcast_i16_to_bf16_inreg(i16 inreg %a, i32 inreg %b) {
179-
; SI-LABEL: s_bitcast_i16_to_bf16_inreg:
178+
define inreg bfloat @s_bitcast_i16_to_bf16(i16 inreg %a, i32 inreg %b) {
179+
; SI-LABEL: s_bitcast_i16_to_bf16:
180180
; SI: ; %bb.0:
181181
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
182182
; SI-NEXT: s_and_b32 s6, s16, 0xffff
@@ -195,7 +195,7 @@ define inreg bfloat @s_bitcast_i16_to_bf16_inreg(i16 inreg %a, i32 inreg %b) {
195195
; SI-NEXT: ; implicit-def: $sgpr7
196196
; SI-NEXT: s_branch .LBB2_2
197197
;
198-
; VI-LABEL: s_bitcast_i16_to_bf16_inreg:
198+
; VI-LABEL: s_bitcast_i16_to_bf16:
199199
; VI: ; %bb.0:
200200
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
201201
; VI-NEXT: s_cmp_lg_u32 s17, 0
@@ -210,7 +210,7 @@ define inreg bfloat @s_bitcast_i16_to_bf16_inreg(i16 inreg %a, i32 inreg %b) {
210210
; VI-NEXT: .LBB2_4:
211211
; VI-NEXT: s_branch .LBB2_2
212212
;
213-
; GFX9-LABEL: s_bitcast_i16_to_bf16_inreg:
213+
; GFX9-LABEL: s_bitcast_i16_to_bf16:
214214
; GFX9: ; %bb.0:
215215
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
216216
; GFX9-NEXT: s_cmp_lg_u32 s17, 0
@@ -225,7 +225,7 @@ define inreg bfloat @s_bitcast_i16_to_bf16_inreg(i16 inreg %a, i32 inreg %b) {
225225
; GFX9-NEXT: .LBB2_4:
226226
; GFX9-NEXT: s_branch .LBB2_2
227227
;
228-
; GFX11-LABEL: s_bitcast_i16_to_bf16_inreg:
228+
; GFX11-LABEL: s_bitcast_i16_to_bf16:
229229
; GFX11: ; %bb.0:
230230
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
231231
; GFX11-NEXT: s_cmp_lg_u32 s1, 0
@@ -260,8 +260,8 @@ end:
260260
ret bfloat %phi
261261
}
262262

263-
define inreg i16 @s_bitcast_bf16_to_i16_inreg(bfloat inreg %a, i32 inreg %b) {
264-
; SI-LABEL: s_bitcast_bf16_to_i16_inreg:
263+
define inreg i16 @s_bitcast_bf16_to_i16(bfloat inreg %a, i32 inreg %b) {
264+
; SI-LABEL: s_bitcast_bf16_to_i16:
265265
; SI: ; %bb.0:
266266
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
267267
; SI-NEXT: s_cmp_lg_u32 s17, 0
@@ -280,7 +280,7 @@ define inreg i16 @s_bitcast_bf16_to_i16_inreg(bfloat inreg %a, i32 inreg %b) {
280280
; SI-NEXT: ; implicit-def: $vgpr0
281281
; SI-NEXT: s_branch .LBB3_2
282282
;
283-
; VI-LABEL: s_bitcast_bf16_to_i16_inreg:
283+
; VI-LABEL: s_bitcast_bf16_to_i16:
284284
; VI: ; %bb.0:
285285
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
286286
; VI-NEXT: s_cmp_lg_u32 s17, 0
@@ -305,7 +305,7 @@ define inreg i16 @s_bitcast_bf16_to_i16_inreg(bfloat inreg %a, i32 inreg %b) {
305305
; VI-NEXT: v_mov_b32_e32 v0, s16
306306
; VI-NEXT: s_setpc_b64 s[30:31]
307307
;
308-
; GFX9-LABEL: s_bitcast_bf16_to_i16_inreg:
308+
; GFX9-LABEL: s_bitcast_bf16_to_i16:
309309
; GFX9: ; %bb.0:
310310
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
311311
; GFX9-NEXT: s_cmp_lg_u32 s17, 0
@@ -330,7 +330,7 @@ define inreg i16 @s_bitcast_bf16_to_i16_inreg(bfloat inreg %a, i32 inreg %b) {
330330
; GFX9-NEXT: v_mov_b32_e32 v0, s16
331331
; GFX9-NEXT: s_setpc_b64 s[30:31]
332332
;
333-
; GFX11-LABEL: s_bitcast_bf16_to_i16_inreg:
333+
; GFX11-LABEL: s_bitcast_bf16_to_i16:
334334
; GFX11: ; %bb.0:
335335
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
336336
; GFX11-NEXT: s_cmp_lg_u32 s1, 0
@@ -375,8 +375,8 @@ end:
375375
ret i16 %phi
376376
}
377377

378-
define inreg bfloat @s_bitcast_f16_to_bf16_inreg(half inreg %a, i32 inreg %b) {
379-
; SI-LABEL: s_bitcast_f16_to_bf16_inreg:
378+
define inreg bfloat @s_bitcast_f16_to_bf16(half inreg %a, i32 inreg %b) {
379+
; SI-LABEL: s_bitcast_f16_to_bf16:
380380
; SI: ; %bb.0:
381381
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
382382
; SI-NEXT: v_cvt_f16_f32_e32 v1, s16
@@ -396,7 +396,7 @@ define inreg bfloat @s_bitcast_f16_to_bf16_inreg(half inreg %a, i32 inreg %b) {
396396
; SI-NEXT: ; implicit-def: $vgpr0
397397
; SI-NEXT: s_branch .LBB4_2
398398
;
399-
; VI-LABEL: s_bitcast_f16_to_bf16_inreg:
399+
; VI-LABEL: s_bitcast_f16_to_bf16:
400400
; VI: ; %bb.0:
401401
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
402402
; VI-NEXT: s_cmp_lg_u32 s17, 0
@@ -413,7 +413,7 @@ define inreg bfloat @s_bitcast_f16_to_bf16_inreg(half inreg %a, i32 inreg %b) {
413413
; VI-NEXT: v_mov_b32_e32 v0, s16
414414
; VI-NEXT: s_setpc_b64 s[30:31]
415415
;
416-
; GFX9-LABEL: s_bitcast_f16_to_bf16_inreg:
416+
; GFX9-LABEL: s_bitcast_f16_to_bf16:
417417
; GFX9: ; %bb.0:
418418
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
419419
; GFX9-NEXT: s_cmp_lg_u32 s17, 0
@@ -430,7 +430,7 @@ define inreg bfloat @s_bitcast_f16_to_bf16_inreg(half inreg %a, i32 inreg %b) {
430430
; GFX9-NEXT: v_mov_b32_e32 v0, s16
431431
; GFX9-NEXT: s_setpc_b64 s[30:31]
432432
;
433-
; GFX11-LABEL: s_bitcast_f16_to_bf16_inreg:
433+
; GFX11-LABEL: s_bitcast_f16_to_bf16:
434434
; GFX11: ; %bb.0:
435435
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
436436
; GFX11-NEXT: s_cmp_lg_u32 s1, 0
@@ -464,8 +464,8 @@ end:
464464
ret bfloat %phi
465465
}
466466

467-
define inreg half @s_bitcast_bf16_to_f16_inreg(bfloat inreg %a, i32 inreg %b) {
468-
; SI-LABEL: s_bitcast_bf16_to_f16_inreg:
467+
define inreg half @s_bitcast_bf16_to_f16(bfloat inreg %a, i32 inreg %b) {
468+
; SI-LABEL: s_bitcast_bf16_to_f16:
469469
; SI: ; %bb.0:
470470
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
471471
; SI-NEXT: s_cmp_lg_u32 s17, 0
@@ -486,7 +486,7 @@ define inreg half @s_bitcast_bf16_to_f16_inreg(bfloat inreg %a, i32 inreg %b) {
486486
; SI-NEXT: ; implicit-def: $vgpr0
487487
; SI-NEXT: s_branch .LBB5_2
488488
;
489-
; VI-LABEL: s_bitcast_bf16_to_f16_inreg:
489+
; VI-LABEL: s_bitcast_bf16_to_f16:
490490
; VI: ; %bb.0:
491491
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
492492
; VI-NEXT: s_cmp_lg_u32 s17, 0
@@ -511,7 +511,7 @@ define inreg half @s_bitcast_bf16_to_f16_inreg(bfloat inreg %a, i32 inreg %b) {
511511
; VI-NEXT: v_mov_b32_e32 v0, s16
512512
; VI-NEXT: s_setpc_b64 s[30:31]
513513
;
514-
; GFX9-LABEL: s_bitcast_bf16_to_f16_inreg:
514+
; GFX9-LABEL: s_bitcast_bf16_to_f16:
515515
; GFX9: ; %bb.0:
516516
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
517517
; GFX9-NEXT: s_cmp_lg_u32 s17, 0
@@ -536,7 +536,7 @@ define inreg half @s_bitcast_bf16_to_f16_inreg(bfloat inreg %a, i32 inreg %b) {
536536
; GFX9-NEXT: v_mov_b32_e32 v0, s16
537537
; GFX9-NEXT: s_setpc_b64 s[30:31]
538538
;
539-
; GFX11-LABEL: s_bitcast_bf16_to_f16_inreg:
539+
; GFX11-LABEL: s_bitcast_bf16_to_f16:
540540
; GFX11: ; %bb.0:
541541
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
542542
; GFX11-NEXT: s_cmp_lg_u32 s1, 0

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