Add missing overlap check, tests for same, and tests for masked forms

Author: preames

llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td

@@ -16,6 +16,7 @@
 
 
 let Predicates = [HasVendorXRivosVizip], DecoderNamespace = "XRivos",
+  Constraints = "@earlyclobber $vd", RVVConstraint = Vrgather,
   Inst<6-0> = OPC_CUSTOM_2.Value in  {
 defm RV_VZIPEVEN_V : VALU_IV_V<"rv.vzipeven", 0b001100>;
 defm RV_VZIPODD_V : VALU_IV_V<"rv.vzipodd", 0b011100>;

llvm/test/MC/RISCV/xrivosvizip-invalid.s

@@ -0,0 +1,10 @@
+# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-xrivosvizip < %s 2>&1 | \
+# RUN:   FileCheck %s
+
+# Disallowed source/dest overlap cases
+# CHECK:  error: the destination vector register group cannot overlap the source vector register group
+rv.vzipeven.vv v2, v2, v3
+# CHECK:  error: the destination vector register group cannot overlap the source vector register group
+rv.vzipeven.vv v3, v2, v3
+# CHECK: error: the destination vector register group cannot overlap the mask register
+rv.vzipeven.vv v0, v2, v3, v0.t

llvm/test/MC/RISCV/xrivosvizip-valid.s

@@ -12,19 +12,48 @@
 # CHECK-ASM-AND-OBJ: rv.vzipeven.vv    v1, v2, v3
 # CHECK-ASM: encoding: [0xdb,0x80,0x21,0x32]
 rv.vzipeven.vv v1, v2, v3
+# CHECK-ASM-AND-OBJ: rv.vzipeven.vv    v1, v2, v3, v0.t
+# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x30]
+rv.vzipeven.vv v1, v2, v3, v0.t
 # CHECK-ASM-AND-OBJ: rv.vzipodd.vv  v1, v2, v3
 # CHECK-ASM: encoding: [0xdb,0x80,0x21,0x72]
 rv.vzipodd.vv v1, v2, v3
+# CHECK-ASM-AND-OBJ: rv.vzipodd.vv  v1, v2, v3, v0.t
+# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x70]
+rv.vzipodd.vv v1, v2, v3, v0.t
+
 # CHECK-ASM-AND-OBJ:  rv.vzip2a.vv   v1, v2, v3
 # CHECK-ASM: encoding: [0xdb,0x80,0x21,0x12]
 rv.vzip2a.vv v1, v2, v3
+# CHECK-ASM-AND-OBJ:  rv.vzip2a.vv   v1, v2, v3, v0.t
+# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x10]
+rv.vzip2a.vv v1, v2, v3, v0.t
 # CHECK-ASM-AND-OBJ: rv.vzip2b.vv   v1, v2, v3
 # CHECK-ASM: encoding: [0xdb,0x80,0x21,0x52]
 rv.vzip2b.vv v1, v2, v3
+# CHECK-ASM-AND-OBJ: rv.vzip2b.vv   v1, v2, v3, v0.t
+# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x50]
+rv.vzip2b.vv v1, v2, v3, v0.t
+
 # CHECK-ASM-AND-OBJ: rv.vunzip2a.vv v1, v2, v3
 # CHECK-ASM: encoding: [0xdb,0x80,0x21,0x22]
 rv.vunzip2a.vv v1, v2, v3
+# CHECK-ASM-AND-OBJ: rv.vunzip2a.vv v1, v2, v3, v0.t
+# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x20]
+rv.vunzip2a.vv v1, v2, v3, v0.t
 # CHECK-ASM-AND-OBJ: rv.vunzip2b.vv v1, v2, v3
 # CHECK-ASM: encoding: [0xdb,0x80,0x21,0x62]
 rv.vunzip2b.vv v1, v2, v3
+# CHECK-ASM-AND-OBJ: rv.vunzip2b.vv v1, v2, v3, v0.t
+# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x60]
+rv.vunzip2b.vv v1, v2, v3, v0.t
+
+# Overlap between source registers *is* allowed
+
+# CHECK-ASM-AND-OBJ: rv.vzipeven.vv    v1, v2, v2
+# CHECK-ASM: encoding: [0xdb,0x00,0x21,0x32]
+rv.vzipeven.vv v1, v2, v2
 
+# CHECK-ASM-AND-OBJ: rv.vzipeven.vv    v1, v2, v0, v0.t
+# CHECK-ASM: encoding: [0xdb,0x00,0x20,0x30]
+rv.vzipeven.vv v1, v2, v0, v0.t