@@ -580,6 +580,15 @@ def __nvvm_f2bf16_rz : NVPTXBuiltinSMAndPTX<"__bf16(float)", SM_80, PTX70>;
580580def __nvvm_f2bf16_rz_relu : NVPTXBuiltinSMAndPTX<" __bf16(float)" , SM_80, PTX70>;
581581
582582def __nvvm_f2tf32_rna : NVPTXBuiltinSMAndPTX<" int32_t(float)" , SM_80, PTX70>;
583+ def __nvvm_f2tf32_rna_satfinite : NVPTXBuiltinSMAndPTX<" int32_t(float)" , SM_89, PTX81>;
584+ def __nvvm_f2tf32_rn : NVPTXBuiltinSMAndPTX<" int32_t(float)" , SM_90, PTX78>;
585+ def __nvvm_f2tf32_rn_relu : NVPTXBuiltinSMAndPTX<" int32_t(float)" , SM_90, PTX78>;
586+ def __nvvm_f2tf32_rn_satfinite : NVPTXBuiltinSMAndPTX<" int32_t(float)" , SM_100, PTX86>;
587+ def __nvvm_f2tf32_rn_relu_satfinite : NVPTXBuiltinSMAndPTX<" int32_t(float)" , SM_100, PTX86>;
588+ def __nvvm_f2tf32_rz : NVPTXBuiltinSMAndPTX<" int32_t(float)" , SM_90, PTX78>;
589+ def __nvvm_f2tf32_rz_relu : NVPTXBuiltinSMAndPTX<" int32_t(float)" , SM_90, PTX78>;
590+ def __nvvm_f2tf32_rz_satfinite : NVPTXBuiltinSMAndPTX<" int32_t(float)" , SM_100, PTX86>;
591+ def __nvvm_f2tf32_rz_relu_satfinite : NVPTXBuiltinSMAndPTX<" int32_t(float)" , SM_100, PTX86>;
583592
584593def __nvvm_ff_to_e4m3x2_rn : NVPTXBuiltinSMAndPTX<" short(float, float)" , SM_89, PTX81>;
585594def __nvvm_ff_to_e4m3x2_rn_relu : NVPTXBuiltinSMAndPTX<" short(float, float)" , SM_89, PTX81>;
@@ -596,6 +605,28 @@ def __nvvm_e4m3x2_to_f16x2_rn_relu : NVPTXBuiltinSMAndPTX<"_Vector<2, __fp16>(sh
596605def __nvvm_e5m2x2_to_f16x2_rn : NVPTXBuiltinSMAndPTX<" _Vector<2, __fp16>(short)" , SM_89, PTX81>;
597606def __nvvm_e5m2x2_to_f16x2_rn_relu : NVPTXBuiltinSMAndPTX<" _Vector<2, __fp16>(short)" , SM_89, PTX81>;
598607
608+ def __nvvm_ff_to_e2m3x2_rn_satfinite : NVPTXBuiltinSMAndPTX<" short(float, float)" , SM<" 100a" , [SM_101a, SM_120a]>, PTX86>;
609+ def __nvvm_ff_to_e2m3x2_rn_relu_satfinite : NVPTXBuiltinSMAndPTX<" short(float, float)" , SM<" 100a" , [SM_101a, SM_120a]>, PTX86>;
610+ def __nvvm_ff_to_e3m2x2_rn_satfinite : NVPTXBuiltinSMAndPTX<" short(float, float)" , SM<" 100a" , [SM_101a, SM_120a]>, PTX86>;
611+ def __nvvm_ff_to_e3m2x2_rn_relu_satfinite : NVPTXBuiltinSMAndPTX<" short(float, float)" , SM<" 100a" , [SM_101a, SM_120a]>, PTX86>;
612+
613+ def __nvvm_e2m3x2_to_f16x2_rn : NVPTXBuiltinSMAndPTX<" _Vector<2, __fp16>(short)" , SM<" 100a" , [SM_101a, SM_120a]>, PTX86>;
614+ def __nvvm_e2m3x2_to_f16x2_rn_relu : NVPTXBuiltinSMAndPTX<" _Vector<2, __fp16>(short)" , SM<" 100a" , [SM_101a, SM_120a]>, PTX86>;
615+ def __nvvm_e3m2x2_to_f16x2_rn : NVPTXBuiltinSMAndPTX<" _Vector<2, __fp16>(short)" , SM<" 100a" , [SM_101a, SM_120a]>, PTX86>;
616+ def __nvvm_e3m2x2_to_f16x2_rn_relu : NVPTXBuiltinSMAndPTX<" _Vector<2, __fp16>(short)" , SM<" 100a" , [SM_101a, SM_120a]>, PTX86>;
617+
618+ def __nvvm_ff_to_ue8m0x2_rz : NVPTXBuiltinSMAndPTX<" short(float, float)" , SM<" 100a" , [SM_101a, SM_120a]>, PTX86>;
619+ def __nvvm_ff_to_ue8m0x2_rz_satfinite : NVPTXBuiltinSMAndPTX<" short(float, float)" , SM<" 100a" , [SM_101a, SM_120a]>, PTX86>;
620+ def __nvvm_ff_to_ue8m0x2_rp : NVPTXBuiltinSMAndPTX<" short(float, float)" , SM<" 100a" , [SM_101a, SM_120a]>, PTX86>;
621+ def __nvvm_ff_to_ue8m0x2_rp_satfinite : NVPTXBuiltinSMAndPTX<" short(float, float)" , SM<" 100a" , [SM_101a, SM_120a]>, PTX86>;
622+
623+ def __nvvm_bf16x2_to_ue8m0x2_rz : NVPTXBuiltinSMAndPTX<" short(_Vector<2, __bf16>)" , SM<" 100a" , [SM_101a, SM_120a]>, PTX86>;
624+ def __nvvm_bf16x2_to_ue8m0x2_rz_satfinite : NVPTXBuiltinSMAndPTX<" short(_Vector<2, __bf16>)" , SM<" 100a" , [SM_101a, SM_120a]>, PTX86>;
625+ def __nvvm_bf16x2_to_ue8m0x2_rp : NVPTXBuiltinSMAndPTX<" short(_Vector<2, __bf16>)" , SM<" 100a" , [SM_101a, SM_120a]>, PTX86>;
626+ def __nvvm_bf16x2_to_ue8m0x2_rp_satfinite : NVPTXBuiltinSMAndPTX<" short(_Vector<2, __bf16>)" , SM<" 100a" , [SM_101a, SM_120a]>, PTX86>;
627+
628+ def __nvvm_ue8m0x2_to_bf16x2 : NVPTXBuiltinSMAndPTX<" _Vector<2, __bf16>(short)" , SM<" 100a" , [SM_101a, SM_120a]>, PTX86>;
629+
599630// FNS
600631let Attributes = [NoThrow] in {
601632 def __nvvm_fns : NVPTXBuiltinPTX<" unsigned int(unsigned int, unsigned int, int)" , PTX60>;
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