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[LLVM][AMDGPU][NFC] clang-format Target/AMDGPU
1 parent 0fdb908 commit f7ff93c

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140 files changed

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‎llvm/lib/Target/AMDGPU/AMDGPU.h‎

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -93,7 +93,7 @@ class SILowerI1CopiesPass : public PassInfoMixin<SILowerI1CopiesPass> {
9393

9494
void initializeAMDGPUDAGToDAGISelLegacyPass(PassRegistry &);
9595

96-
void initializeAMDGPUAlwaysInlinePass(PassRegistry&);
96+
void initializeAMDGPUAlwaysInlinePass(PassRegistry &);
9797

9898
Pass *createAMDGPUAttributorLegacyPass();
9999
void initializeAMDGPUAttributorLegacyPass(PassRegistry &);
@@ -233,11 +233,11 @@ extern char &AMDGPUPreloadKernArgPrologLegacyID;
233233

234234
// Passes common to R600 and SI
235235
FunctionPass *createAMDGPUPromoteAlloca();
236-
void initializeAMDGPUPromoteAllocaPass(PassRegistry&);
236+
void initializeAMDGPUPromoteAllocaPass(PassRegistry &);
237237
extern char &AMDGPUPromoteAllocaID;
238238

239239
FunctionPass *createAMDGPUPromoteAllocaToVector();
240-
void initializeAMDGPUPromoteAllocaToVectorPass(PassRegistry&);
240+
void initializeAMDGPUPromoteAllocaToVectorPass(PassRegistry &);
241241
extern char &AMDGPUPromoteAllocaToVectorID;
242242

243243
struct AMDGPUPromoteAllocaPass : PassInfoMixin<AMDGPUPromoteAllocaPass> {
@@ -302,7 +302,7 @@ class AMDGPUCodeGenPreparePass
302302
TargetMachine &TM;
303303

304304
public:
305-
AMDGPUCodeGenPreparePass(TargetMachine &TM) : TM(TM){};
305+
AMDGPUCodeGenPreparePass(TargetMachine &TM) : TM(TM) {};
306306
PreservedAnalyses run(Function &, FunctionAnalysisManager &);
307307
};
308308

@@ -322,7 +322,7 @@ class AMDGPULowerKernelArgumentsPass
322322
TargetMachine &TM;
323323

324324
public:
325-
AMDGPULowerKernelArgumentsPass(TargetMachine &TM) : TM(TM){};
325+
AMDGPULowerKernelArgumentsPass(TargetMachine &TM) : TM(TM) {};
326326
PreservedAnalyses run(Function &, FunctionAnalysisManager &);
327327
};
328328

@@ -413,7 +413,7 @@ class AMDGPUSetWavePriorityPass
413413
FunctionPass *createAMDGPUAnnotateUniformValuesLegacy();
414414

415415
ModulePass *createAMDGPUPrintfRuntimeBinding();
416-
void initializeAMDGPUPrintfRuntimeBindingPass(PassRegistry&);
416+
void initializeAMDGPUPrintfRuntimeBindingPass(PassRegistry &);
417417
extern char &AMDGPUPrintfRuntimeBindingID;
418418

419419
void initializeAMDGPUResourceUsageAnalysisPass(PassRegistry &);
@@ -424,8 +424,8 @@ struct AMDGPUPrintfRuntimeBindingPass
424424
PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
425425
};
426426

427-
ModulePass* createAMDGPUUnifyMetadataPass();
428-
void initializeAMDGPUUnifyMetadataPass(PassRegistry&);
427+
ModulePass *createAMDGPUUnifyMetadataPass();
428+
void initializeAMDGPUUnifyMetadataPass(PassRegistry &);
429429
extern char &AMDGPUUnifyMetadataID;
430430

431431
struct AMDGPUUnifyMetadataPass : PassInfoMixin<AMDGPUUnifyMetadataPass> {
@@ -441,7 +441,7 @@ extern char &SIOptimizeVGPRLiveRangeLegacyID;
441441
void initializeAMDGPUAnnotateUniformValuesLegacyPass(PassRegistry &);
442442
extern char &AMDGPUAnnotateUniformValuesLegacyPassID;
443443

444-
void initializeAMDGPUCodeGenPreparePass(PassRegistry&);
444+
void initializeAMDGPUCodeGenPreparePass(PassRegistry &);
445445
extern char &AMDGPUCodeGenPrepareID;
446446

447447
void initializeAMDGPURemoveIncompatibleFunctionsLegacyPass(PassRegistry &);
@@ -498,13 +498,13 @@ extern char &SIPostRABundlerLegacyID;
498498
void initializeGCNCreateVOPDLegacyPass(PassRegistry &);
499499
extern char &GCNCreateVOPDID;
500500

501-
void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry&);
501+
void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry &);
502502
extern char &AMDGPUUnifyDivergentExitNodesID;
503503

504504
ImmutablePass *createAMDGPUAAWrapperPass();
505-
void initializeAMDGPUAAWrapperPassPass(PassRegistry&);
505+
void initializeAMDGPUAAWrapperPassPass(PassRegistry &);
506506
ImmutablePass *createAMDGPUExternalAAWrapperPass();
507-
void initializeAMDGPUExternalAAWrapperPass(PassRegistry&);
507+
void initializeAMDGPUExternalAAWrapperPass(PassRegistry &);
508508

509509
void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &);
510510

@@ -565,7 +565,7 @@ static inline bool addrspacesMayAlias(unsigned AS1, unsigned AS2) {
565565
return ASAliasRules[AS1][AS2];
566566
}
567567

568-
}
568+
} // namespace AMDGPU
569569

570570
} // End namespace llvm
571571

‎llvm/lib/Target/AMDGPU/AMDGPUAliasAnalysis.cpp‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -28,7 +28,8 @@ INITIALIZE_PASS(AMDGPUAAWrapperPass, "amdgpu-aa",
2828
"AMDGPU Address space based Alias Analysis", false, true)
2929

3030
INITIALIZE_PASS(AMDGPUExternalAAWrapper, "amdgpu-aa-wrapper",
31-
"AMDGPU Address space based Alias Analysis Wrapper", false, true)
31+
"AMDGPU Address space based Alias Analysis Wrapper", false,
32+
true)
3233

3334
ImmutablePass *llvm::createAMDGPUAAWrapperPass() {
3435
return new AMDGPUAAWrapperPass();

‎llvm/lib/Target/AMDGPU/AMDGPUAliasAnalysis.h‎

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -88,11 +88,12 @@ class AMDGPUExternalAAWrapper : public ExternalAAWrapperPass {
8888
public:
8989
static char ID;
9090

91-
AMDGPUExternalAAWrapper() : ExternalAAWrapperPass(
92-
[](Pass &P, Function &, AAResults &AAR) {
93-
if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
94-
AAR.addAAResult(WrapperPass->getResult());
95-
}) {}
91+
AMDGPUExternalAAWrapper()
92+
: ExternalAAWrapperPass([](Pass &P, Function &, AAResults &AAR) {
93+
if (auto *WrapperPass =
94+
P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
95+
AAR.addAAResult(WrapperPass->getResult());
96+
}) {}
9697
};
9798

9899
} // end namespace llvm

‎llvm/lib/Target/AMDGPU/AMDGPUAlwaysInlinePass.cpp‎

Lines changed: 10 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -24,20 +24,18 @@ using namespace llvm;
2424

2525
namespace {
2626

27-
static cl::opt<bool> StressCalls(
28-
"amdgpu-stress-function-calls",
29-
cl::Hidden,
30-
cl::desc("Force all functions to be noinline"),
31-
cl::init(false));
27+
static cl::opt<bool> StressCalls("amdgpu-stress-function-calls", cl::Hidden,
28+
cl::desc("Force all functions to be noinline"),
29+
cl::init(false));
3230

3331
class AMDGPUAlwaysInline : public ModulePass {
3432
bool GlobalOpt;
3533

3634
public:
3735
static char ID;
3836

39-
AMDGPUAlwaysInline(bool GlobalOpt = false) :
40-
ModulePass(ID), GlobalOpt(GlobalOpt) { }
37+
AMDGPUAlwaysInline(bool GlobalOpt = false)
38+
: ModulePass(ID), GlobalOpt(GlobalOpt) {}
4139
bool runOnModule(Module &M) override;
4240

4341
void getAnalysisUsage(AnalysisUsage &AU) const override {
@@ -87,15 +85,15 @@ recursivelyVisitUsers(GlobalValue &GV,
8785
}
8886

8987
static bool alwaysInlineImpl(Module &M, bool GlobalOpt) {
90-
std::vector<GlobalAlias*> AliasesToRemove;
88+
std::vector<GlobalAlias *> AliasesToRemove;
9189

9290
bool Changed = false;
9391
SmallPtrSet<Function *, 8> FuncsToAlwaysInline;
9492
SmallPtrSet<Function *, 8> FuncsToNoInline;
9593
Triple TT(M.getTargetTriple());
9694

9795
for (GlobalAlias &A : M.aliases()) {
98-
if (Function* F = dyn_cast<Function>(A.getAliasee())) {
96+
if (Function *F = dyn_cast<Function>(A.getAliasee())) {
9997
if (TT.isAMDGCN() && A.getLinkage() != GlobalValue::InternalLinkage)
10098
continue;
10199
Changed = true;
@@ -108,7 +106,7 @@ static bool alwaysInlineImpl(Module &M, bool GlobalOpt) {
108106
}
109107

110108
if (GlobalOpt) {
111-
for (GlobalAlias* A : AliasesToRemove) {
109+
for (GlobalAlias *A : AliasesToRemove) {
112110
A->eraseFromParent();
113111
}
114112
}
@@ -133,8 +131,8 @@ static bool alwaysInlineImpl(Module &M, bool GlobalOpt) {
133131
}
134132

135133
if (!AMDGPUTargetMachine::EnableFunctionCalls || StressCalls) {
136-
auto IncompatAttr
137-
= StressCalls ? Attribute::AlwaysInline : Attribute::NoInline;
134+
auto IncompatAttr =
135+
StressCalls ? Attribute::AlwaysInline : Attribute::NoInline;
138136

139137
for (Function &F : M) {
140138
if (!F.isDeclaration() && !F.use_empty() &&

‎llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.cpp‎

Lines changed: 9 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -47,12 +47,10 @@ char AMDGPUArgumentUsageInfo::ID = 0;
4747
const AMDGPUFunctionArgInfo AMDGPUArgumentUsageInfo::ExternFunctionInfo{};
4848

4949
// Hardcoded registers from fixed function ABI
50-
const AMDGPUFunctionArgInfo AMDGPUArgumentUsageInfo::FixedABIFunctionInfo
51-
= AMDGPUFunctionArgInfo::fixedABILayout();
50+
const AMDGPUFunctionArgInfo AMDGPUArgumentUsageInfo::FixedABIFunctionInfo =
51+
AMDGPUFunctionArgInfo::fixedABILayout();
5252

53-
bool AMDGPUArgumentUsageInfo::doInitialization(Module &M) {
54-
return false;
55-
}
53+
bool AMDGPUArgumentUsageInfo::doInitialization(Module &M) { return false; }
5654

5755
bool AMDGPUArgumentUsageInfo::doFinalization(Module &M) {
5856
ArgInfoMap.clear();
@@ -76,13 +74,11 @@ void AMDGPUArgumentUsageInfo::print(raw_ostream &OS, const Module *M) const {
7674
<< " WorkGroupInfo: " << FI.second.WorkGroupInfo
7775
<< " LDSKernelId: " << FI.second.LDSKernelId
7876
<< " PrivateSegmentWaveByteOffset: "
79-
<< FI.second.PrivateSegmentWaveByteOffset
77+
<< FI.second.PrivateSegmentWaveByteOffset
8078
<< " ImplicitBufferPtr: " << FI.second.ImplicitBufferPtr
81-
<< " ImplicitArgPtr: " << FI.second.ImplicitArgPtr
82-
<< " WorkItemIDX " << FI.second.WorkItemIDX
83-
<< " WorkItemIDY " << FI.second.WorkItemIDY
84-
<< " WorkItemIDZ " << FI.second.WorkItemIDZ
85-
<< '\n';
79+
<< " ImplicitArgPtr: " << FI.second.ImplicitArgPtr << " WorkItemIDX "
80+
<< FI.second.WorkItemIDX << " WorkItemIDY " << FI.second.WorkItemIDY
81+
<< " WorkItemIDZ " << FI.second.WorkItemIDZ << '\n';
8682
}
8783
}
8884

@@ -153,8 +149,8 @@ AMDGPUFunctionArgInfo::getPreloadedValue(
153149

154150
AMDGPUFunctionArgInfo AMDGPUFunctionArgInfo::fixedABILayout() {
155151
AMDGPUFunctionArgInfo AI;
156-
AI.PrivateSegmentBuffer
157-
= ArgDescriptor::createRegister(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3);
152+
AI.PrivateSegmentBuffer =
153+
ArgDescriptor::createRegister(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3);
158154
AI.DispatchPtr = ArgDescriptor::createRegister(AMDGPU::SGPR4_SGPR5);
159155
AI.QueuePtr = ArgDescriptor::createRegister(AMDGPU::SGPR6_SGPR7);
160156

‎llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.h‎

Lines changed: 5 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -55,17 +55,11 @@ struct ArgDescriptor {
5555
return ArgDescriptor(Arg.Reg, Mask, Arg.IsStack, Arg.IsSet);
5656
}
5757

58-
bool isSet() const {
59-
return IsSet;
60-
}
58+
bool isSet() const { return IsSet; }
6159

62-
explicit operator bool() const {
63-
return isSet();
64-
}
60+
explicit operator bool() const { return isSet(); }
6561

66-
bool isRegister() const {
67-
return !IsStack;
68-
}
62+
bool isRegister() const { return !IsStack; }
6963

7064
MCRegister getRegister() const {
7165
assert(!IsStack);
@@ -83,9 +77,7 @@ struct ArgDescriptor {
8377
return Mask;
8478
}
8579

86-
bool isMasked() const {
87-
return Mask != ~0u;
88-
}
80+
bool isMasked() const { return Mask != ~0u; }
8981

9082
void print(raw_ostream &OS, const TargetRegisterInfo *TRI = nullptr) const;
9183
};
@@ -181,7 +173,7 @@ class AMDGPUArgumentUsageInfo : public ImmutablePass {
181173
static const AMDGPUFunctionArgInfo ExternFunctionInfo;
182174
static const AMDGPUFunctionArgInfo FixedABIFunctionInfo;
183175

184-
AMDGPUArgumentUsageInfo() : ImmutablePass(ID) { }
176+
AMDGPUArgumentUsageInfo() : ImmutablePass(ID) {}
185177

186178
void getAnalysisUsage(AnalysisUsage &AU) const override {
187179
AU.setPreservesAll();

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