[AMDGPU] Optimize out s_barrier_signal/_wait

Extend the optimization that converts s_barrier to wave_barrier (nop)
when the number of work items is not larger than wave size.

This handles the "split barrier" form of s_barrier where the barrier
is represented by separate intrinsics (s_barrier_signal/s_barrier_wait).
Note: the version where s_barrier is used in gfx12 (and later split)
has the optimization already, but some front-ends may prefer to use
split intrinsics and this is being addressed by the patch.

Author: piotrAMD

llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

@@ -1843,8 +1843,9 @@ bool AMDGPUInstructionSelector::selectSBarrier(MachineInstr &MI) const {
     }
   }
 
-  // On GFX12 lower s_barrier into s_barrier_signal_imm and s_barrier_wait
-  if (STI.hasSplitBarriers()) {
+  Intrinsic::ID IntrinsicID = cast<GIntrinsic>(MI).getIntrinsicID();
+  if (STI.hasSplitBarriers() && IntrinsicID == Intrinsic::amdgcn_s_barrier) {
+    // On GFX12 lower s_barrier into s_barrier_signal_imm and s_barrier_wait
     MachineBasicBlock *MBB = MI.getParent();
     const DebugLoc &DL = MI.getDebugLoc();
     BuildMI(*MBB, &MI, DL, TII.get(AMDGPU::S_BARRIER_SIGNAL_IMM))
@@ -2161,6 +2162,8 @@ bool AMDGPUInstructionSelector::selectG_INTRINSIC_W_SIDE_EFFECTS(
   case Intrinsic::amdgcn_init_whole_wave:
     return selectInitWholeWave(I);
   case Intrinsic::amdgcn_s_barrier:
+  case Intrinsic::amdgcn_s_barrier_signal:
+  case Intrinsic::amdgcn_s_barrier_wait:
     return selectSBarrier(I);
   case Intrinsic::amdgcn_raw_buffer_load_lds:
   case Intrinsic::amdgcn_raw_ptr_buffer_load_lds:

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

@@ -9605,7 +9605,9 @@ SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op,
     unsigned Opc = Done->isZero() ? AMDGPU::EXP : AMDGPU::EXP_DONE;
     return SDValue(DAG.getMachineNode(Opc, DL, Op->getVTList(), Ops), 0);
   }
-  case Intrinsic::amdgcn_s_barrier: {
+  case Intrinsic::amdgcn_s_barrier:
+  case Intrinsic::amdgcn_s_barrier_signal:
+  case Intrinsic::amdgcn_s_barrier_wait: {
     const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
     if (getTargetMachine().getOptLevel() > CodeGenOptLevel::None) {
       unsigned WGSize = ST.getFlatWorkGroupSizes(MF.getFunction()).second;
@@ -9615,8 +9617,8 @@ SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op,
                        0);
     }
 
-    // On GFX12 lower s_barrier into s_barrier_signal_imm and s_barrier_wait
-    if (ST.hasSplitBarriers()) {
+    if (ST.hasSplitBarriers() && IntrinsicID == Intrinsic::amdgcn_s_barrier) {
+      // On GFX12 lower s_barrier into s_barrier_signal_imm and s_barrier_wait
       SDValue K =
           DAG.getTargetConstant(AMDGPU::Barrier::WORKGROUP, DL, MVT::i32);
       SDValue BarSignal =

llvm/test/CodeGen/AMDGPU/barrier-elimination-gfx12.ll

@@ -16,7 +16,9 @@ define amdgpu_kernel void @signal_flat_wgs_attr_32_128() #1 {
 }
 
 ; CHECK-LABEL: {{^}}signal_flat_wgs_attr_32_64:
-; CHECK: s_barrier_signal
+; CHECK: :
+; CHECK-NEXT: ; wave barrier
+; CHECK-NEXT: s_endpgm
 define amdgpu_kernel void @signal_flat_wgs_attr_32_64() #2 {
   tail call void @llvm.amdgcn.s.barrier.signal(i32 -1) #0
   ret void
@@ -39,7 +41,8 @@ define amdgpu_kernel void @wait_flat_wgs_attr_32_128() #1 {
 
 ; CHECK-LABEL: {{^}}wait_flat_wgs_attr_32_64:
 ; CHECK: :
-; CHECK-NEXT: s_barrier_wait
+; CHECK-NEXT: ; wave barrier
+; CHECK-NEXT: s_endpgm
 define amdgpu_kernel void @wait_flat_wgs_attr_32_64() #2 {
   tail call void @llvm.amdgcn.s.barrier.wait(i16 -1) #0
   ret void