Skip to content

Commit f83218c

Browse files
SubashBoopathiSubashBoopathi
committed
Experimental Constrained Conversion intrinsics
1 parent ea7d2c2 commit f83218c

File tree

4 files changed

+182
-170
lines changed

4 files changed

+182
-170
lines changed

‎llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2090,7 +2090,7 @@ static unsigned getConstrainedOpcode(Intrinsic::ID ID) {
20902090
return TargetOpcode::G_STRICT_FPTOUI;
20912091
case Intrinsic::experimental_constrained_fpext:
20922092
return TargetOpcode::G_STRICT_FPEXT;
2093-
case Intrinsic::experimental_constrained_fptrunc:
2093+
case Intrinsic::experimental_constrained_fptrunc:
20942094
return TargetOpcode::G_STRICT_FPTRUNC;
20952095
default:
20962096
return 0;

‎llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp‎

Lines changed: 5 additions & 120 deletions
Original file line numberDiff line numberDiff line change
@@ -229,22 +229,6 @@ class SPIRVInstructionSelector : public InstructionSelector {
229229
MachineInstr &I, bool IsSigned) const;
230230
bool selectIToF(Register ResVReg, const SPIRVType *ResType, MachineInstr &I,
231231
bool IsSigned, unsigned Opcode) const;
232-
233-
bool selectStrictSIToF(Register ResVReg, const SPIRVType *ResType,
234-
MachineInstr &I) const;
235-
236-
bool selectStrictUIToF(Register ResVReg, const SPIRVType *ResType,
237-
MachineInstr &I) const;
238-
239-
bool selectStrictFPToS(Register ResVReg, const SPIRVType *ResType,
240-
MachineInstr &I) const;
241-
242-
bool selectStrictFPToU(Register ResVReg, const SPIRVType *ResType,
243-
MachineInstr &I) const;
244-
245-
bool selectStrictFPEXT(Register ResVReg, const SPIRVType *ResType,
246-
MachineInstr &I) const;
247-
248232
bool selectExt(Register ResVReg, const SPIRVType *ResType, MachineInstr &I,
249233
bool IsSigned) const;
250234

@@ -709,16 +693,16 @@ bool SPIRVInstructionSelector::spvSelect(Register ResVReg,
709693
return selectIToF(ResVReg, ResType, I, false, SPIRV::OpConvertUToF);
710694

711695
case TargetOpcode::G_STRICT_SITOFP:
712-
return selectStrictSIToF(ResVReg, ResType, I);
696+
return selectUnOp(ResVReg, ResType, I, SPIRV::OpConvertSToF);
713697
case TargetOpcode::G_STRICT_UITOFP:
714-
return selectStrictUIToF(ResVReg, ResType, I);
698+
return selectUnOp(ResVReg, ResType, I, SPIRV::OpConvertUToF);
715699
case TargetOpcode::G_STRICT_FPTOSI:
716-
return selectStrictFPToS(ResVReg, ResType, I);
700+
return selectUnOp(ResVReg, ResType, I, SPIRV::OpConvertFToS);
717701
case TargetOpcode::G_STRICT_FPTOUI:
718-
return selectStrictFPToU(ResVReg, ResType, I);
702+
return selectUnOp(ResVReg, ResType, I, SPIRV::OpConvertFToU);
719703
case TargetOpcode::G_STRICT_FPEXT:
720704
case TargetOpcode::G_STRICT_FPTRUNC:
721-
return selectStrictFPEXT(ResVReg, ResType, I);
705+
return selectUnOp(ResVReg, ResType, I, SPIRV::OpFConvert);
722706

723707
case TargetOpcode::G_CTPOP:
724708
return selectUnOp(ResVReg, ResType, I, SPIRV::OpBitCount);
@@ -2681,105 +2665,6 @@ bool SPIRVInstructionSelector::selectSelectDefaultArgs(Register ResVReg,
26812665
.addUse(ZeroReg)
26822666
.constrainAllUses(TII, TRI, RBI);
26832667
}
2684-
bool SPIRVInstructionSelector::selectStrictSIToF(Register ResVReg,
2685-
const SPIRVType *ResType,
2686-
MachineInstr &I) const {
2687-
// Convert a signed integer to a floating-point value using OpConvertSToF.
2688-
// If the source is a boolean, first convert it to an integer of matching bit
2689-
// width.
2690-
Register SrcReg = I.getOperand(1).getReg();
2691-
if (GR.isScalarOrVectorOfType(SrcReg, SPIRV::OpTypeBool)) {
2692-
unsigned BitWidth = GR.getScalarOrVectorBitWidth(ResType);
2693-
SPIRVType *TmpType = GR.getOrCreateSPIRVIntegerType(BitWidth, I, TII);
2694-
if (ResType->getOpcode() == SPIRV::OpTypeVector) {
2695-
const unsigned NumElts = ResType->getOperand(2).getImm();
2696-
TmpType = GR.getOrCreateSPIRVVectorType(TmpType, NumElts, I, TII);
2697-
}
2698-
SrcReg = createVirtualRegister(TmpType, &GR, MRI, MRI->getMF());
2699-
selectSelect(SrcReg, TmpType, I, false);
2700-
}
2701-
return selectOpWithSrcs(ResVReg, ResType, I, {SrcReg}, SPIRV::OpConvertSToF);
2702-
}
2703-
2704-
bool SPIRVInstructionSelector::selectStrictUIToF(Register ResVReg,
2705-
const SPIRVType *ResType,
2706-
MachineInstr &I) const {
2707-
// Convert an unsigned integer to a floating-point value using OpConvertUToF.
2708-
// If the source is a boolean, first convert it to an integer of matching bit
2709-
// width.
2710-
Register SrcReg = I.getOperand(1).getReg();
2711-
if (GR.isScalarOrVectorOfType(SrcReg, SPIRV::OpTypeBool)) {
2712-
unsigned BitWidth = GR.getScalarOrVectorBitWidth(ResType);
2713-
SPIRVType *TmpType = GR.getOrCreateSPIRVIntegerType(BitWidth, I, TII);
2714-
if (ResType->getOpcode() == SPIRV::OpTypeVector) {
2715-
const unsigned NumElts = ResType->getOperand(2).getImm();
2716-
TmpType = GR.getOrCreateSPIRVVectorType(TmpType, NumElts, I, TII);
2717-
}
2718-
SrcReg = createVirtualRegister(TmpType, &GR, MRI, MRI->getMF());
2719-
selectSelect(SrcReg, TmpType, I, false);
2720-
}
2721-
return selectOpWithSrcs(ResVReg, ResType, I, {SrcReg}, SPIRV::OpConvertUToF);
2722-
}
2723-
2724-
bool SPIRVInstructionSelector::selectStrictFPToS(Register ResVReg,
2725-
const SPIRVType *ResType,
2726-
MachineInstr &I) const {
2727-
// Convert a floating-point value to a signed integer using OpConvertFToS.
2728-
// If the source is a boolean, first convert it to a float of matching bit
2729-
// width.
2730-
Register SrcReg = I.getOperand(1).getReg();
2731-
if (GR.isScalarOrVectorOfType(SrcReg, SPIRV::OpTypeBool)) {
2732-
unsigned BitWidth = GR.getScalarOrVectorBitWidth(ResType);
2733-
SPIRVType *TmpType = GR.getOrCreateSPIRVFloatType(BitWidth, I, TII);
2734-
if (ResType->getOpcode() == SPIRV::OpTypeVector) {
2735-
const unsigned NumElts = ResType->getOperand(2).getImm();
2736-
TmpType = GR.getOrCreateSPIRVVectorType(TmpType, NumElts, I, TII);
2737-
}
2738-
SrcReg = createVirtualRegister(TmpType, &GR, MRI, MRI->getMF());
2739-
selectSelect(SrcReg, TmpType, I, false);
2740-
}
2741-
return selectOpWithSrcs(ResVReg, ResType, I, {SrcReg}, SPIRV::OpConvertFToS);
2742-
}
2743-
2744-
bool SPIRVInstructionSelector::selectStrictFPToU(Register ResVReg,
2745-
const SPIRVType *ResType,
2746-
MachineInstr &I) const {
2747-
// Convert a floating-point value to an unsigned integer using OpConvertFToU.
2748-
// If the source is a boolean, first convert it to a float of matching bit
2749-
// width.
2750-
Register SrcReg = I.getOperand(1).getReg();
2751-
if (GR.isScalarOrVectorOfType(SrcReg, SPIRV::OpTypeBool)) {
2752-
unsigned BitWidth = GR.getScalarOrVectorBitWidth(ResType);
2753-
SPIRVType *TmpType = GR.getOrCreateSPIRVFloatType(BitWidth, I, TII);
2754-
if (ResType->getOpcode() == SPIRV::OpTypeVector) {
2755-
const unsigned NumElts = ResType->getOperand(2).getImm();
2756-
TmpType = GR.getOrCreateSPIRVVectorType(TmpType, NumElts, I, TII);
2757-
}
2758-
SrcReg = createVirtualRegister(TmpType, &GR, MRI, MRI->getMF());
2759-
selectSelect(SrcReg, TmpType, I, false);
2760-
}
2761-
return selectOpWithSrcs(ResVReg, ResType, I, {SrcReg}, SPIRV::OpConvertFToU);
2762-
}
2763-
2764-
bool SPIRVInstructionSelector::selectStrictFPEXT(Register ResVReg,
2765-
const SPIRVType *ResType,
2766-
MachineInstr &I) const {
2767-
// Extend a floating-point value to a larger floating-point type using
2768-
// OpFConvert. If the source is a boolean, first convert it to a float of
2769-
// matching bit width.
2770-
Register SrcReg = I.getOperand(1).getReg();
2771-
if (GR.isScalarOrVectorOfType(SrcReg, SPIRV::OpTypeBool)) {
2772-
unsigned BitWidth = GR.getScalarOrVectorBitWidth(ResType);
2773-
SPIRVType *TmpType = GR.getOrCreateSPIRVFloatType(BitWidth, I, TII);
2774-
if (ResType->getOpcode() == SPIRV::OpTypeVector) {
2775-
const unsigned NumElts = ResType->getOperand(2).getImm();
2776-
TmpType = GR.getOrCreateSPIRVVectorType(TmpType, NumElts, I, TII);
2777-
}
2778-
SrcReg = createVirtualRegister(TmpType, &GR, MRI, MRI->getMF());
2779-
selectSelect(SrcReg, TmpType, I, false);
2780-
}
2781-
return selectOpWithSrcs(ResVReg, ResType, I, {SrcReg}, SPIRV::OpFConvert);
2782-
}
27832668

27842669
bool SPIRVInstructionSelector::selectIToF(Register ResVReg,
27852670
const SPIRVType *ResType,

‎llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -60,7 +60,7 @@ SPIRVLegalizerInfo::SPIRVLegalizerInfo(const SPIRVSubtarget &ST) {
6060
const LLT v4s16 = LLT::fixed_vector(4, 16);
6161
const LLT v4s8 = LLT::fixed_vector(4, 8);
6262
const LLT v4s1 = LLT::fixed_vector(4, 1);
63-
63+
6464
const LLT v3s64 = LLT::fixed_vector(3, 64);
6565
const LLT v3s32 = LLT::fixed_vector(3, 32);
6666
const LLT v3s16 = LLT::fixed_vector(3, 16);
@@ -209,7 +209,7 @@ SPIRVLegalizerInfo::SPIRVLegalizerInfo(const SPIRVSubtarget &ST) {
209209

210210
getActionDefinitionsBuilder({G_STRICT_SITOFP, G_STRICT_UITOFP})
211211
.legalForCartesianProduct(allFloatScalarsAndVectors,
212-
allScalarsAndVectors);
212+
allIntScalarsAndVectors);
213213

214214
getActionDefinitionsBuilder({G_STRICT_FPTOSI, G_STRICT_FPTOUI})
215215
.legalForCartesianProduct(allIntScalarsAndVectors,

0 commit comments

Comments
 (0)