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AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select (#153174)
1 parent 1d30f71 commit f88be47

35 files changed

+334
-348
lines changed

llvm/test/CodeGen/AMDGPU/GlobalISel/add_shl.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=fiji < %s | FileCheck -check-prefix=VI %s
3-
; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
4-
; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
5-
; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefix=GFX10 %s
2+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-mesa3d -mcpu=fiji < %s | FileCheck -check-prefix=VI %s
3+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
4+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
5+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefix=GFX10 %s
66

77
; ===================================================================================
88
; V_ADD_LSHL_U32

llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.i1.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2-
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefix=WAVE64 %s
3-
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck -check-prefix=WAVE32 %s
2+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefix=WAVE64 %s
3+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck -check-prefix=WAVE32 %s
44

55
define i32 @s_andn2_i1_vcc(i32 %arg0, i32 %arg1) {
66
; WAVE64-LABEL: s_andn2_i1_vcc:

llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-asserts.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1031 < %s | FileCheck %s
2+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1031 < %s | FileCheck %s
33

44
define hidden <2 x i64> @icmp_v2i32_sext_to_v2i64(<2 x i32> %arg) {
55
; CHECK-LABEL: icmp_v2i32_sext_to_v2i64:

llvm/test/CodeGen/AMDGPU/GlobalISel/br-constant-invalid-sgpr-copy.ll

Lines changed: 10 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -global-isel -O0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=WAVE64 %s
3-
; RUN: llc -global-isel -O0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1031 < %s | FileCheck -check-prefix=WAVE32 %s
2+
; RUN: llc -global-isel -new-reg-bank-select -O0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=WAVE64 %s
3+
; RUN: llc -global-isel -new-reg-bank-select -O0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1031 < %s | FileCheck -check-prefix=WAVE32 %s
44

55
; This was mishandling the constant true and false values used as a
66
; scalar branch condition.
@@ -76,7 +76,8 @@ define void @br_undef() {
7676
; WAVE64-NEXT: .LBB2_1: ; %bb0
7777
; WAVE64-NEXT: ; =>This Inner Loop Header: Depth=1
7878
; WAVE64-NEXT: ; implicit-def: $sgpr4
79-
; WAVE64-NEXT: s_and_b32 s4, s4, 1
79+
; WAVE64-NEXT: s_mov_b32 s5, 1
80+
; WAVE64-NEXT: s_and_b32 s4, s4, s5
8081
; WAVE64-NEXT: s_cmp_lg_u32 s4, 0
8182
; WAVE64-NEXT: s_cbranch_scc1 .LBB2_1
8283
; WAVE64-NEXT: ; %bb.2: ; %.exit5
@@ -88,7 +89,8 @@ define void @br_undef() {
8889
; WAVE32-NEXT: .LBB2_1: ; %bb0
8990
; WAVE32-NEXT: ; =>This Inner Loop Header: Depth=1
9091
; WAVE32-NEXT: ; implicit-def: $sgpr4
91-
; WAVE32-NEXT: s_and_b32 s4, s4, 1
92+
; WAVE32-NEXT: s_mov_b32 s5, 1
93+
; WAVE32-NEXT: s_and_b32 s4, s4, s5
9294
; WAVE32-NEXT: s_cmp_lg_u32 s4, 0
9395
; WAVE32-NEXT: s_cbranch_scc1 .LBB2_1
9496
; WAVE32-NEXT: ; %bb.2: ; %.exit5
@@ -110,7 +112,8 @@ define void @br_poison() {
110112
; WAVE64-NEXT: .LBB3_1: ; %bb0
111113
; WAVE64-NEXT: ; =>This Inner Loop Header: Depth=1
112114
; WAVE64-NEXT: ; implicit-def: $sgpr4
113-
; WAVE64-NEXT: s_and_b32 s4, s4, 1
115+
; WAVE64-NEXT: s_mov_b32 s5, 1
116+
; WAVE64-NEXT: s_and_b32 s4, s4, s5
114117
; WAVE64-NEXT: s_cmp_lg_u32 s4, 0
115118
; WAVE64-NEXT: s_cbranch_scc1 .LBB3_1
116119
; WAVE64-NEXT: ; %bb.2: ; %.exit5
@@ -122,7 +125,8 @@ define void @br_poison() {
122125
; WAVE32-NEXT: .LBB3_1: ; %bb0
123126
; WAVE32-NEXT: ; =>This Inner Loop Header: Depth=1
124127
; WAVE32-NEXT: ; implicit-def: $sgpr4
125-
; WAVE32-NEXT: s_and_b32 s4, s4, 1
128+
; WAVE32-NEXT: s_mov_b32 s5, 1
129+
; WAVE32-NEXT: s_and_b32 s4, s4, s5
126130
; WAVE32-NEXT: s_cmp_lg_u32 s4, 0
127131
; WAVE32-NEXT: s_cbranch_scc1 .LBB3_1
128132
; WAVE32-NEXT: ; %bb.2: ; %.exit5

llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -global-isel -mtriple=amdgcn < %s | FileCheck %s
2+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn < %s | FileCheck %s
33

44
define amdgpu_cs i32 @test_shl_1(i32 inreg %arg1) {
55
; CHECK-LABEL: test_shl_1:

llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-of-shifted-logic.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -global-isel -mtriple=amdgcn < %s | FileCheck %s
2+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn < %s | FileCheck %s
33

44
define amdgpu_cs i32 @test_shl_and_1(i32 inreg %arg1) {
55
; CHECK-LABEL: test_shl_and_1:

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