@@ -211,10 +211,10 @@ static bool isMaskOperand(const MachineInstr &MI, const MachineOperand &MO,
211211 return Desc.operands ()[MO.getOperandNo ()].RegClass == RISCV::VMV0RegClassID;
212212}
213213
214- // / Return the OperandInfo for MO, which is an operand of MI.
215- static OperandInfo getOperandInfo (const MachineInstr &MI,
216- const MachineOperand &MO,
214+ // / Return the OperandInfo for MO.
215+ static OperandInfo getOperandInfo (const MachineOperand &MO,
217216 const MachineRegisterInfo *MRI) {
217+ const MachineInstr &MI = *MO.getParent ();
218218 const RISCVVPseudosTable::PseudoInfo *RVV =
219219 RISCVVPseudosTable::getPseudoInfo (MI.getOpcode ());
220220 assert (RVV && " Could not find MI in PseudoTable" );
@@ -942,8 +942,8 @@ bool RISCVVLOptimizer::checkUsers(const MachineOperand *&CommonVL,
942942 assert (isVectorRegClass (UserMI.getOperand (0 ).getReg (), MRI) &&
943943 " Expected DEF and USE to be vector registers" );
944944
945- OperandInfo ConsumerInfo = getOperandInfo (UserMI, UserOp, MRI);
946- OperandInfo ProducerInfo = getOperandInfo (MI, MI .getOperand (0 ), MRI);
945+ OperandInfo ConsumerInfo = getOperandInfo (UserOp, MRI);
946+ OperandInfo ProducerInfo = getOperandInfo (MI.getOperand (0 ), MRI);
947947 if (ConsumerInfo.isUnknown () || ProducerInfo.isUnknown () ||
948948 !OperandInfo::EMULAndEEWAreEqual (ConsumerInfo, ProducerInfo)) {
949949 LLVM_DEBUG (dbgs () << " Abort due to incompatible or unknown "
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