chack for scalable vectors

Author: Hardcode84

mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPU.td

@@ -38,7 +38,7 @@ def AMDGPU_Dialect : Dialect {
 def AnyIntegerOrFloat : AnyTypeOf<[AnySignlessInteger, AnyFloat], "Integer or Float">;
 
 def AnyIntegerOrFloatOr1DVector :
-  AnyTypeOf<[AnyIntegerOrFloat, VectorOfRankAndType<[1], [AnyIntegerOrFloat]>]>;
+  AnyTypeOf<[AnyIntegerOrFloat, FixedVectorOfRankAndType<[1], [AnyIntegerOrFloat]>]>;
 
 //===----------------------------------------------------------------------===//
 // AMDGPU general attribute definitions

mlir/lib/Conversion/LLVMCommon/Pattern.cpp

@@ -387,6 +387,7 @@ static unsigned getBitWidth(Type type) {
     return type.getIntOrFloatBitWidth();
 
   auto vec = cast<VectorType>(type);
+  assert(!vec.isScalable() && "scalable vectors are not supported");
   return vec.getNumElements() * getBitWidth(vec.getElementType());
 }
 

mlir/test/Dialect/AMDGPU/invalid.mlir

@@ -154,7 +154,15 @@ func.func @fat_raw_buffer_cast_stripping_offset_affine_map(%m: memref<8xi32, aff
 // -----
 
 func.func @swizzle_invalid_type(%arg0 : si32) -> si32 {
-  // expected-error@+1 {{amdgpu.swizzle_bitmode' op operand #0 must be Integer or Float or vector of Integer or Float values of ranks 1}}
+  // expected-error@+1 {{'amdgpu.swizzle_bitmode' op operand #0 must be Integer or Float or fixed-length vector of Integer or Float values of ranks 1}}
   %0 = amdgpu.swizzle_bitmode %arg0 1 2 4 : si32
   func.return %0 : si32
 }
+
+// -----
+
+func.func @swizzle_scalable_vec(%arg0 : vector<[4]xf32>) -> vector<[4]xf32> {
+  // expected-error@+1 {{'amdgpu.swizzle_bitmode' op operand #0 must be Integer or Float or fixed-length vector of Integer or Float values of ranks 1}}
+  %0 = amdgpu.swizzle_bitmode %arg0 1 2 4 : vector<[4]xf32>
+  func.return %0 : vector<[4]xf32>
+}