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[clang][wasm] Replace the target integer sub saturate intrinsics with the equivalent generic __builtin_elementwise_sub_sat intrinsics (#109405)
Remove the Intrinsic::wasm_sub_sat_signed/wasm_sub_sat_unsigned entries and just use sub_sat_s/sub_sat_u directly
1 parent 0074cea commit f8f0a26

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9 files changed

+21
-86
lines changed

9 files changed

+21
-86
lines changed

‎clang/include/clang/Basic/BuiltinsWebAssembly.def‎

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -68,11 +68,6 @@ TARGET_BUILTIN(__builtin_wasm_trunc_saturate_u_i64_f64, "LLid", "nc", "nontrappi
6868
// SIMD builtins
6969
TARGET_BUILTIN(__builtin_wasm_swizzle_i8x16, "V16ScV16ScV16Sc", "nc", "simd128")
7070

71-
TARGET_BUILTIN(__builtin_wasm_sub_sat_s_i8x16, "V16ScV16ScV16Sc", "nc", "simd128")
72-
TARGET_BUILTIN(__builtin_wasm_sub_sat_u_i8x16, "V16UcV16UcV16Uc", "nc", "simd128")
73-
TARGET_BUILTIN(__builtin_wasm_sub_sat_s_i16x8, "V8sV8sV8s", "nc", "simd128")
74-
TARGET_BUILTIN(__builtin_wasm_sub_sat_u_i16x8, "V8UsV8UsV8Us", "nc", "simd128")
75-
7671
TARGET_BUILTIN(__builtin_wasm_abs_i8x16, "V16ScV16Sc", "nc", "simd128")
7772
TARGET_BUILTIN(__builtin_wasm_abs_i16x8, "V8sV8s", "nc", "simd128")
7873
TARGET_BUILTIN(__builtin_wasm_abs_i32x4, "V4iV4i", "nc", "simd128")

‎clang/lib/CodeGen/CGBuiltin.cpp‎

Lines changed: 0 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -21443,28 +21443,6 @@ Value *CodeGenFunction::EmitWebAssemblyBuiltinExpr(unsigned BuiltinID,
2144321443
Function *Callee = CGM.getIntrinsic(Intrinsic::wasm_swizzle);
2144421444
return Builder.CreateCall(Callee, {Src, Indices});
2144521445
}
21446-
case WebAssembly::BI__builtin_wasm_sub_sat_s_i8x16:
21447-
case WebAssembly::BI__builtin_wasm_sub_sat_u_i8x16:
21448-
case WebAssembly::BI__builtin_wasm_sub_sat_s_i16x8:
21449-
case WebAssembly::BI__builtin_wasm_sub_sat_u_i16x8: {
21450-
unsigned IntNo;
21451-
switch (BuiltinID) {
21452-
case WebAssembly::BI__builtin_wasm_sub_sat_s_i8x16:
21453-
case WebAssembly::BI__builtin_wasm_sub_sat_s_i16x8:
21454-
IntNo = Intrinsic::wasm_sub_sat_signed;
21455-
break;
21456-
case WebAssembly::BI__builtin_wasm_sub_sat_u_i8x16:
21457-
case WebAssembly::BI__builtin_wasm_sub_sat_u_i16x8:
21458-
IntNo = Intrinsic::wasm_sub_sat_unsigned;
21459-
break;
21460-
default:
21461-
llvm_unreachable("unexpected builtin ID");
21462-
}
21463-
Value *LHS = EmitScalarExpr(E->getArg(0));
21464-
Value *RHS = EmitScalarExpr(E->getArg(1));
21465-
Function *Callee = CGM.getIntrinsic(IntNo, ConvertType(E->getType()));
21466-
return Builder.CreateCall(Callee, {LHS, RHS});
21467-
}
2146821446
case WebAssembly::BI__builtin_wasm_abs_i8x16:
2146921447
case WebAssembly::BI__builtin_wasm_abs_i16x8:
2147021448
case WebAssembly::BI__builtin_wasm_abs_i32x4:

‎clang/lib/Headers/wasm_simd128.h‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -997,12 +997,12 @@ static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i8x16_sub(v128_t __a,
997997

998998
static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i8x16_sub_sat(v128_t __a,
999999
v128_t __b) {
1000-
return (v128_t)__builtin_wasm_sub_sat_s_i8x16((__i8x16)__a, (__i8x16)__b);
1000+
return (v128_t)__builtin_elementwise_sub_sat((__i8x16)__a, (__i8x16)__b);
10011001
}
10021002

10031003
static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_u8x16_sub_sat(v128_t __a,
10041004
v128_t __b) {
1005-
return (v128_t)__builtin_wasm_sub_sat_u_i8x16((__u8x16)__a, (__u8x16)__b);
1005+
return (v128_t)__builtin_elementwise_sub_sat((__u8x16)__a, (__u8x16)__b);
10061006
}
10071007

10081008
static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i8x16_min(v128_t __a,
@@ -1083,12 +1083,12 @@ static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i16x8_sub(v128_t __a,
10831083

10841084
static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i16x8_sub_sat(v128_t __a,
10851085
v128_t __b) {
1086-
return (v128_t)__builtin_wasm_sub_sat_s_i16x8((__i16x8)__a, (__i16x8)__b);
1086+
return (v128_t)__builtin_elementwise_sub_sat((__i16x8)__a, (__i16x8)__b);
10871087
}
10881088

10891089
static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_u16x8_sub_sat(v128_t __a,
10901090
v128_t __b) {
1091-
return (v128_t)__builtin_wasm_sub_sat_u_i16x8((__u16x8)__a, (__u16x8)__b);
1091+
return (v128_t)__builtin_elementwise_sub_sat((__u16x8)__a, (__u16x8)__b);
10921092
}
10931093

10941094
static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i16x8_mul(v128_t __a,

‎clang/test/CodeGen/builtins-wasm.c‎

Lines changed: 1 addition & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -190,23 +190,9 @@ double max_f64(double x, double y) {
190190
// WEBASSEMBLY-NEXT: ret
191191
}
192192

193-
i8x16 sub_sat_s_i8x16(i8x16 x, i8x16 y) {
194-
return __builtin_wasm_sub_sat_s_i8x16(x, y);
195-
// MISSING-SIMD: error: '__builtin_wasm_sub_sat_s_i8x16' needs target feature simd128
196-
// WEBASSEMBLY: call <16 x i8> @llvm.wasm.sub.sat.signed.v16i8(
197-
// WEBASSEMBLY-SAME: <16 x i8> %x, <16 x i8> %y)
198-
// WEBASSEMBLY-NEXT: ret
199-
}
200-
201-
u8x16 sub_sat_u_i8x16(u8x16 x, u8x16 y) {
202-
return __builtin_wasm_sub_sat_u_i8x16(x, y);
203-
// WEBASSEMBLY: call <16 x i8> @llvm.wasm.sub.sat.unsigned.v16i8(
204-
// WEBASSEMBLY-SAME: <16 x i8> %x, <16 x i8> %y)
205-
// WEBASSEMBLY-NEXT: ret
206-
}
207-
208193
i8x16 abs_i8x16(i8x16 v) {
209194
return __builtin_wasm_abs_i8x16(v);
195+
// MISSING-SIMD: error: '__builtin_wasm_abs_i8x16' needs target feature simd128
210196
// WEBASSEMBLY: call <16 x i8> @llvm.abs.v16i8(<16 x i8> %v, i1 false)
211197
// WEBASSEMBLY-NEXT: ret
212198
}
@@ -229,20 +215,6 @@ i64x2 abs_i64x2(i64x2 v) {
229215
// WEBASSEMBLY-NEXT: ret
230216
}
231217

232-
i16x8 sub_sat_s_i16x8(i16x8 x, i16x8 y) {
233-
return __builtin_wasm_sub_sat_s_i16x8(x, y);
234-
// WEBASSEMBLY: call <8 x i16> @llvm.wasm.sub.sat.signed.v8i16(
235-
// WEBASSEMBLY-SAME: <8 x i16> %x, <8 x i16> %y)
236-
// WEBASSEMBLY-NEXT: ret
237-
}
238-
239-
u16x8 sub_sat_u_i16x8(u16x8 x, u16x8 y) {
240-
return __builtin_wasm_sub_sat_u_i16x8(x, y);
241-
// WEBASSEMBLY: call <8 x i16> @llvm.wasm.sub.sat.unsigned.v8i16(
242-
// WEBASSEMBLY-SAME: <8 x i16> %x, <8 x i16> %y)
243-
// WEBASSEMBLY-NEXT: ret
244-
}
245-
246218
u8x16 avgr_u_i8x16(u8x16 x, u8x16 y) {
247219
return __builtin_wasm_avgr_u_i8x16(x, y);
248220
// WEBASSEMBLY: call <16 x i8> @llvm.wasm.avgr.unsigned.v16i8(

‎clang/test/Headers/wasm.c‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1677,7 +1677,7 @@ v128_t test_i8x16_sub(v128_t a, v128_t b) {
16771677
// CHECK-NEXT: entry:
16781678
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <16 x i8>
16791679
// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B:%.*]] to <16 x i8>
1680-
// CHECK-NEXT: [[TMP2:%.*]] = tail call <16 x i8> @llvm.wasm.sub.sat.signed.v16i8(<16 x i8> [[TMP0]], <16 x i8> [[TMP1]])
1680+
// CHECK-NEXT: [[TMP2:%.*]] = tail call <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8> [[TMP0]], <16 x i8> [[TMP1]])
16811681
// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP2]] to <4 x i32>
16821682
// CHECK-NEXT: ret <4 x i32> [[TMP3]]
16831683
//
@@ -1689,7 +1689,7 @@ v128_t test_i8x16_sub_sat(v128_t a, v128_t b) {
16891689
// CHECK-NEXT: entry:
16901690
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <16 x i8>
16911691
// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B:%.*]] to <16 x i8>
1692-
// CHECK-NEXT: [[TMP2:%.*]] = tail call <16 x i8> @llvm.wasm.sub.sat.unsigned.v16i8(<16 x i8> [[TMP0]], <16 x i8> [[TMP1]])
1692+
// CHECK-NEXT: [[TMP2:%.*]] = tail call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> [[TMP0]], <16 x i8> [[TMP1]])
16931693
// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP2]] to <4 x i32>
16941694
// CHECK-NEXT: ret <4 x i32> [[TMP3]]
16951695
//
@@ -1897,7 +1897,7 @@ v128_t test_i16x8_sub(v128_t a, v128_t b) {
18971897
// CHECK-NEXT: entry:
18981898
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <8 x i16>
18991899
// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B:%.*]] to <8 x i16>
1900-
// CHECK-NEXT: [[TMP2:%.*]] = tail call <8 x i16> @llvm.wasm.sub.sat.signed.v8i16(<8 x i16> [[TMP0]], <8 x i16> [[TMP1]])
1900+
// CHECK-NEXT: [[TMP2:%.*]] = tail call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> [[TMP0]], <8 x i16> [[TMP1]])
19011901
// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[TMP2]] to <4 x i32>
19021902
// CHECK-NEXT: ret <4 x i32> [[TMP3]]
19031903
//
@@ -1909,7 +1909,7 @@ v128_t test_i16x8_sub_sat(v128_t a, v128_t b) {
19091909
// CHECK-NEXT: entry:
19101910
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <8 x i16>
19111911
// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B:%.*]] to <8 x i16>
1912-
// CHECK-NEXT: [[TMP2:%.*]] = tail call <8 x i16> @llvm.wasm.sub.sat.unsigned.v8i16(<8 x i16> [[TMP0]], <8 x i16> [[TMP1]])
1912+
// CHECK-NEXT: [[TMP2:%.*]] = tail call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> [[TMP0]], <8 x i16> [[TMP1]])
19131913
// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[TMP2]] to <4 x i32>
19141914
// CHECK-NEXT: ret <4 x i32> [[TMP3]]
19151915
//

‎llvm/include/llvm/IR/IntrinsicsWebAssembly.td‎

Lines changed: 0 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -202,14 +202,6 @@ def int_wasm_shuffle :
202202
ImmArg<ArgIndex<12>>, ImmArg<ArgIndex<13>>,
203203
ImmArg<ArgIndex<14>>, ImmArg<ArgIndex<15>>,
204204
ImmArg<ArgIndex<16>>, ImmArg<ArgIndex<17>>]>;
205-
def int_wasm_sub_sat_signed :
206-
DefaultAttrsIntrinsic<[llvm_anyvector_ty],
207-
[LLVMMatchType<0>, LLVMMatchType<0>],
208-
[IntrNoMem, IntrSpeculatable]>;
209-
def int_wasm_sub_sat_unsigned :
210-
DefaultAttrsIntrinsic<[llvm_anyvector_ty],
211-
[LLVMMatchType<0>, LLVMMatchType<0>],
212-
[IntrNoMem, IntrSpeculatable]>;
213205
def int_wasm_avgr_unsigned :
214206
DefaultAttrsIntrinsic<[llvm_anyvector_ty],
215207
[LLVMMatchType<0>, LLVMMatchType<0>],

‎llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -198,8 +198,8 @@ WebAssemblyTargetLowering::WebAssemblyTargetLowering(
198198

199199
setTargetDAGCombine(ISD::TRUNCATE);
200200

201-
// Support saturating add for i8x16 and i16x8
202-
for (auto Op : {ISD::SADDSAT, ISD::UADDSAT})
201+
// Support saturating add/sub for i8x16 and i16x8
202+
for (auto Op : {ISD::SADDSAT, ISD::UADDSAT, ISD::SSUBSAT, ISD::USUBSAT})
203203
for (auto T : {MVT::v16i8, MVT::v8i16})
204204
setOperationAction(Op, T, Legal);
205205

‎llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td‎

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1112,10 +1112,8 @@ defm ADD_SAT_U : SIMDBinaryIntSmall<uaddsat, "add_sat_u", 112>;
11121112

11131113
// Integer subtraction: sub / sub_sat_s / sub_sat_u
11141114
defm SUB : SIMDBinaryInt<sub, "sub", 113>;
1115-
defm SUB_SAT_S :
1116-
SIMDBinaryIntSmall<int_wasm_sub_sat_signed, "sub_sat_s", 114>;
1117-
defm SUB_SAT_U :
1118-
SIMDBinaryIntSmall<int_wasm_sub_sat_unsigned, "sub_sat_u", 115>;
1115+
defm SUB_SAT_S : SIMDBinaryIntSmall<ssubsat, "sub_sat_s", 114>;
1116+
defm SUB_SAT_U : SIMDBinaryIntSmall<usubsat, "sub_sat_u", 115>;
11191117

11201118
// Integer multiplication: mul
11211119
let isCommutable = 1 in

‎llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -44,9 +44,9 @@ define <16 x i8> @add_sat_u_v16i8(<16 x i8> %x, <16 x i8> %y) {
4444
; CHECK-NEXT: .functype sub_sat_s_v16i8 (v128, v128) -> (v128){{$}}
4545
; CHECK-NEXT: i8x16.sub_sat_s $push[[R:[0-9]+]]=, $0, $1{{$}}
4646
; CHECK-NEXT: return $pop[[R]]{{$}}
47-
declare <16 x i8> @llvm.wasm.sub.sat.signed.v16i8(<16 x i8>, <16 x i8>)
47+
declare <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8>, <16 x i8>)
4848
define <16 x i8> @sub_sat_s_v16i8(<16 x i8> %x, <16 x i8> %y) {
49-
%a = call <16 x i8> @llvm.wasm.sub.sat.signed.v16i8(
49+
%a = call <16 x i8> @llvm.ssub.sat.v16i8(
5050
<16 x i8> %x, <16 x i8> %y
5151
)
5252
ret <16 x i8> %a
@@ -56,9 +56,9 @@ define <16 x i8> @sub_sat_s_v16i8(<16 x i8> %x, <16 x i8> %y) {
5656
; CHECK-NEXT: .functype sub_sat_u_v16i8 (v128, v128) -> (v128){{$}}
5757
; CHECK-NEXT: i8x16.sub_sat_u $push[[R:[0-9]+]]=, $0, $1{{$}}
5858
; CHECK-NEXT: return $pop[[R]]{{$}}
59-
declare <16 x i8> @llvm.wasm.sub.sat.unsigned.v16i8(<16 x i8>, <16 x i8>)
59+
declare <16 x i8> @llvm.usub.sat.v16i8(<16 x i8>, <16 x i8>)
6060
define <16 x i8> @sub_sat_u_v16i8(<16 x i8> %x, <16 x i8> %y) {
61-
%a = call <16 x i8> @llvm.wasm.sub.sat.unsigned.v16i8(
61+
%a = call <16 x i8> @llvm.usub.sat.v16i8(
6262
<16 x i8> %x, <16 x i8> %y
6363
)
6464
ret <16 x i8> %a
@@ -216,9 +216,9 @@ define <8 x i16> @add_sat_u_v8i16(<8 x i16> %x, <8 x i16> %y) {
216216
; CHECK-NEXT: .functype sub_sat_s_v8i16 (v128, v128) -> (v128){{$}}
217217
; CHECK-NEXT: i16x8.sub_sat_s $push[[R:[0-9]+]]=, $0, $1{{$}}
218218
; CHECK-NEXT: return $pop[[R]]{{$}}
219-
declare <8 x i16> @llvm.wasm.sub.sat.signed.v8i16(<8 x i16>, <8 x i16>)
219+
declare <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16>, <8 x i16>)
220220
define <8 x i16> @sub_sat_s_v8i16(<8 x i16> %x, <8 x i16> %y) {
221-
%a = call <8 x i16> @llvm.wasm.sub.sat.signed.v8i16(
221+
%a = call <8 x i16> @llvm.ssub.sat.v8i16(
222222
<8 x i16> %x, <8 x i16> %y
223223
)
224224
ret <8 x i16> %a
@@ -228,9 +228,9 @@ define <8 x i16> @sub_sat_s_v8i16(<8 x i16> %x, <8 x i16> %y) {
228228
; CHECK-NEXT: .functype sub_sat_u_v8i16 (v128, v128) -> (v128){{$}}
229229
; CHECK-NEXT: i16x8.sub_sat_u $push[[R:[0-9]+]]=, $0, $1{{$}}
230230
; CHECK-NEXT: return $pop[[R]]{{$}}
231-
declare <8 x i16> @llvm.wasm.sub.sat.unsigned.v8i16(<8 x i16>, <8 x i16>)
231+
declare <8 x i16> @llvm.usub.sat.v8i16(<8 x i16>, <8 x i16>)
232232
define <8 x i16> @sub_sat_u_v8i16(<8 x i16> %x, <8 x i16> %y) {
233-
%a = call <8 x i16> @llvm.wasm.sub.sat.unsigned.v8i16(
233+
%a = call <8 x i16> @llvm.usub.sat.v8i16(
234234
<8 x i16> %x, <8 x i16> %y
235235
)
236236
ret <8 x i16> %a

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