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llvm/lib/Target/PowerPC/PPCISelLowering.cpp

Lines changed: 6 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1355,19 +1355,18 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
13551355
setOperationAction(ISD::STORE, MVT::v256i1, Custom);
13561356
}
13571357
if (Subtarget.hasMMA()) {
1358-
if (Subtarget.isISAFuture())
1358+
if (Subtarget.isISAFuture()) {
13591359
addRegisterClass(MVT::v512i1, &PPC::WACCRCRegClass);
1360-
else
1360+
addRegisterClass(MVT::v1024i1, &PPC::DMRRCRegClass);
1361+
setOperationAction(ISD::LOAD, MVT::v1024i1, Custom);
1362+
setOperationAction(ISD::STORE, MVT::v1024i1, Custom);
1363+
} else {
13611364
addRegisterClass(MVT::v512i1, &PPC::UACCRCRegClass);
1365+
}
13621366
setOperationAction(ISD::LOAD, MVT::v512i1, Custom);
13631367
setOperationAction(ISD::STORE, MVT::v512i1, Custom);
13641368
setOperationAction(ISD::BUILD_VECTOR, MVT::v512i1, Custom);
13651369
}
1366-
if (Subtarget.isISAFuture()) {
1367-
setOperationAction(ISD::LOAD, MVT::v1024i1, Custom);
1368-
setOperationAction(ISD::STORE, MVT::v1024i1, Custom);
1369-
addRegisterClass(MVT::v1024i1, &PPC::DMRRCRegClass);
1370-
}
13711370

13721371
if (Subtarget.has64BitSupport())
13731372
setOperationAction(ISD::PREFETCH, MVT::Other, Legal);

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