@@ -521,6 +521,32 @@ mlir::LogicalResult CIRToLLVMBitCtzOpLowering::matchAndRewrite(
521521 return mlir::LogicalResult::success ();
522522}
523523
524+ mlir::LogicalResult CIRToLLVMBitFfsOpLowering::matchAndRewrite (
525+ cir::BitFfsOp op, OpAdaptor adaptor,
526+ mlir::ConversionPatternRewriter &rewriter) const {
527+ auto resTy = getTypeConverter ()->convertType (op.getType ());
528+ auto ctz = rewriter.create <mlir::LLVM::CountTrailingZerosOp>(
529+ op.getLoc (), resTy, adaptor.getInput (), /* is_zero_poison=*/ true );
530+
531+ auto one = rewriter.create <mlir::LLVM::ConstantOp>(op.getLoc (), resTy, 1 );
532+ auto ctzAddOne = rewriter.create <mlir::LLVM::AddOp>(op.getLoc (), ctz, one);
533+
534+ auto zeroInputTy = rewriter.create <mlir::LLVM::ConstantOp>(
535+ op.getLoc (), adaptor.getInput ().getType (), 0 );
536+ auto isZero = rewriter.create <mlir::LLVM::ICmpOp>(
537+ op.getLoc (),
538+ mlir::LLVM::ICmpPredicateAttr::get (rewriter.getContext (),
539+ mlir::LLVM::ICmpPredicate::eq),
540+ adaptor.getInput (), zeroInputTy);
541+
542+ auto zero = rewriter.create <mlir::LLVM::ConstantOp>(op.getLoc (), resTy, 0 );
543+ auto res = rewriter.create <mlir::LLVM::SelectOp>(op.getLoc (), isZero, zero,
544+ ctzAddOne);
545+ rewriter.replaceOp (op, res);
546+
547+ return mlir::LogicalResult::success ();
548+ }
549+
524550mlir::LogicalResult CIRToLLVMBitParityOpLowering::matchAndRewrite (
525551 cir::BitParityOp op, OpAdaptor adaptor,
526552 mlir::ConversionPatternRewriter &rewriter) const {
@@ -2089,6 +2115,7 @@ void ConvertCIRToLLVMPass::runOnOperation() {
20892115 CIRToLLVMBitClrsbOpLowering,
20902116 CIRToLLVMBitClzOpLowering,
20912117 CIRToLLVMBitCtzOpLowering,
2118+ CIRToLLVMBitFfsOpLowering,
20922119 CIRToLLVMBitParityOpLowering,
20932120 CIRToLLVMBitPopcountOpLowering,
20942121 CIRToLLVMBitReverseOpLowering,
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