[ARM] Set isCheapToSpeculateCtlz and isCheapToSpeculateCttz as true for hasV5TOps and no Thumb 1

This is so that we don't expand to include unneeded 0 checks.

Also fix the logic error in LegalizerInfo so it is NOT legal on Thumb1 in Fast-ISEL.

Finally, Remove the README entry regarding this issue.

Author: AZero13

llvm/lib/Target/ARM/ARMISelLowering.cpp

@@ -21394,11 +21394,11 @@ bool ARMTargetLowering::canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
 }
 
 bool ARMTargetLowering::isCheapToSpeculateCttz(Type *Ty) const {
-  return Subtarget->hasV6T2Ops();
+  return Subtarget->hasV5TOps() && !Subtarget->isThumb1Only();
 }
 
 bool ARMTargetLowering::isCheapToSpeculateCtlz(Type *Ty) const {
-  return Subtarget->hasV6T2Ops();
+  return Subtarget->hasV5TOps() && !Subtarget->isThumb1Only();
 }
 
 bool ARMTargetLowering::isMaskAndCmp0FoldingBeneficial(

llvm/lib/Target/ARM/ARMLegalizerInfo.cpp

@@ -206,7 +206,7 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) : ST(ST) {
 
   getActionDefinitionsBuilder({G_FREM, G_FPOW}).libcallFor({s32, s64});
 
-  if (ST.hasV5TOps()) {
+  if (ST.hasV5TOps() && !ST.isThumb1Only()) {
     getActionDefinitionsBuilder(G_CTLZ)
         .legalFor({s32, s32})
         .clampScalar(1, s32, s32)

llvm/lib/Target/ARM/README.txt

@@ -697,22 +697,6 @@ target-neutral one.
 
 //===---------------------------------------------------------------------===//
 
-Optimize unnecessary checks for zero with __builtin_clz/ctz.  Those builtins
-are specified to be undefined at zero, so portable code must check for zero
-and handle it as a special case.  That is unnecessary on ARM where those
-operations are implemented in a way that is well-defined for zero.  For
-example:
-
-int f(int x) { return x ? __builtin_clz(x) : sizeof(int)*8; }
-
-should just be implemented with a CLZ instruction.  Since there are other
-targets, e.g., PPC, that share this behavior, it would be best to implement
-this in a target-independent way: we should probably fold that (when using
-"undefined at zero" semantics) to set the "defined at zero" bit and have
-the code generator expand out the right code.
-
-//===---------------------------------------------------------------------===//
-
 Clean up the test/MC/ARM files to have more robust register choices.
 
 R0 should not be used as a register operand in the assembler tests as it's then

llvm/test/CodeGen/ARM/clz.ll

@@ -1,22 +1,26 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
 ; RUN: llc -mtriple=arm-eabi -mattr=+v5t %s -o - | FileCheck %s -check-prefixes=CHECK,INLINE
 ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s -check-prefixes=CHECK,LIBCALL
 
 declare i32 @llvm.ctlz.i32(i32, i1)
 
-define i32 @test(i32 %x) {
-; CHECK-LABEL: test
-; INLINE: clz r0, r0
-; LIBCALL: b __clzsi2
+define i32 @undef_zero(i32 %x) {
+; INLINE-LABEL: undef_zero:
+; INLINE:       @ %bb.0:
+; INLINE-NEXT:    clz r0, r0
+; INLINE-NEXT:    bx lr
+;
+; LIBCALL-LABEL: undef_zero:
+; LIBCALL:       @ %bb.0:
+; LIBCALL-NEXT:    b __clzsi2
         %tmp.1 = call i32 @llvm.ctlz.i32( i32 %x, i1 true )
         ret i32 %tmp.1
 }
 
 define i32 @no_undef_zero(i32 %x) {
 ; INLINE-LABEL: no_undef_zero:
 ; INLINE:       @ %bb.0:
-; INLINE-NEXT:    cmp r0, #0
-; INLINE-NEXT:    clzne r0, r0
-; INLINE-NEXT:    moveq r0, #32
+; INLINE-NEXT:    clz r0, r0
 ; INLINE-NEXT:    bx lr
 ;
 ; LIBCALL-LABEL: no_undef_zero:

llvm/test/CodeGen/ARM/cttz.ll

@@ -17,12 +17,11 @@ declare i64 @llvm.cttz.i64(i64, i1)
 define i8 @test_i8(i8 %a) {
 ; CHECK-5-LABEL: test_i8:
 ; CHECK-5:       @ %bb.0:
-; CHECK-5-NEXT:    tst r0, #255
-; CHECK-5-NEXT:    moveq r0, #8
-; CHECK-5-NEXT:    subne r1, r0, #1
-; CHECK-5-NEXT:    bicne r0, r1, r0
-; CHECK-5-NEXT:    clzne r0, r0
-; CHECK-5-NEXT:    rsbne r0, r0, #32
+; CHECK-5-NEXT:    orr r0, r0, #256
+; CHECK-5-NEXT:    sub r1, r0, #1
+; CHECK-5-NEXT:    bic r0, r1, r0
+; CHECK-5-NEXT:    clz r0, r0
+; CHECK-5-NEXT:    rsb r0, r0, #32
 ; CHECK-5-NEXT:    bx lr
 ;
 ; CHECK-LABEL: test_i8:
@@ -94,14 +93,11 @@ define i8 @test_i8(i8 %a) {
 define i16 @test_i16(i16 %a) {
 ; CHECK-5-LABEL: test_i16:
 ; CHECK-5:       @ %bb.0:
-; CHECK-5-NEXT:    mov r1, #255
-; CHECK-5-NEXT:    orr r1, r1, #65280
-; CHECK-5-NEXT:    tst r0, r1
-; CHECK-5-NEXT:    moveq r0, #16
-; CHECK-5-NEXT:    subne r1, r0, #1
-; CHECK-5-NEXT:    bicne r0, r1, r0
-; CHECK-5-NEXT:    clzne r0, r0
-; CHECK-5-NEXT:    rsbne r0, r0, #32
+; CHECK-5-NEXT:    orr r0, r0, #65536
+; CHECK-5-NEXT:    sub r1, r0, #1
+; CHECK-5-NEXT:    bic r0, r1, r0
+; CHECK-5-NEXT:    clz r0, r0
+; CHECK-5-NEXT:    rsb r0, r0, #32
 ; CHECK-5-NEXT:    bx lr
 ;
 ; CHECK-LABEL: test_i16:
@@ -173,12 +169,10 @@ define i16 @test_i16(i16 %a) {
 define i32 @test_i32(i32 %a) {
 ; CHECK-5-LABEL: test_i32:
 ; CHECK-5:       @ %bb.0:
-; CHECK-5-NEXT:    cmp r0, #0
-; CHECK-5-NEXT:    moveq r0, #32
-; CHECK-5-NEXT:    subne r1, r0, #1
-; CHECK-5-NEXT:    bicne r0, r1, r0
-; CHECK-5-NEXT:    clzne r0, r0
-; CHECK-5-NEXT:    rsbne r0, r0, #32
+; CHECK-5-NEXT:    sub r1, r0, #1
+; CHECK-5-NEXT:    bic r0, r1, r0
+; CHECK-5-NEXT:    clz r0, r0
+; CHECK-5-NEXT:    rsb r0, r0, #32
 ; CHECK-5-NEXT:    bx lr
 ;
 ; CHECK-LABEL: test_i32:
@@ -242,22 +236,17 @@ define i32 @test_i32(i32 %a) {
 define i64 @test_i64(i64 %a) {
 ; CHECK-5-LABEL: test_i64:
 ; CHECK-5:       @ %bb.0:
-; CHECK-5-NEXT:    mov r2, r1
-; CHECK-5-NEXT:    orrs r1, r0, r1
-; CHECK-5-NEXT:    mov r1, #0
-; CHECK-5-NEXT:    moveq r0, #64
-; CHECK-5-NEXT:    bxeq lr
-; CHECK-5-NEXT:  .LBB3_1: @ %cond.false
-; CHECK-5-NEXT:    sub r3, r0, #1
-; CHECK-5-NEXT:    bic r3, r3, r0
-; CHECK-5-NEXT:    clz r12, r3
-; CHECK-5-NEXT:    sub r3, r2, #1
-; CHECK-5-NEXT:    bic r2, r3, r2
-; CHECK-5-NEXT:    mov r3, r0
+; CHECK-5-NEXT:    sub r3, r1, #1
+; CHECK-5-NEXT:    sub r2, r0, #1
+; CHECK-5-NEXT:    bic r1, r3, r1
+; CHECK-5-NEXT:    bic r2, r2, r0
+; CHECK-5-NEXT:    clz r1, r1
 ; CHECK-5-NEXT:    clz r2, r2
-; CHECK-5-NEXT:    cmp r3, #0
-; CHECK-5-NEXT:    rsb r0, r2, #64
-; CHECK-5-NEXT:    rsbne r0, r12, #32
+; CHECK-5-NEXT:    rsb r1, r1, #64
+; CHECK-5-NEXT:    cmp r0, #0
+; CHECK-5-NEXT:    rsbne r1, r2, #32
+; CHECK-5-NEXT:    mov r0, r1
+; CHECK-5-NEXT:    mov r1, #0
 ; CHECK-5-NEXT:    bx lr
 ;
 ; CHECK-LABEL: test_i64: