Skip to content

Commit fb18dcb

Browse files
wangpc-ppwangpc-pp
committed
[𝘀𝗽𝗿] initial version
Created using spr 1.3.6-beta.1
2 parents 9685681 + 42b7aa6 commit fb18dcb

File tree

10 files changed

+252
-12
lines changed

10 files changed

+252
-12
lines changed

‎clang/lib/Basic/Targets/RISCV.cpp‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -508,3 +508,11 @@ bool RISCVTargetInfo::validateGlobalRegisterVariable(
508508
}
509509
return false;
510510
}
511+
512+
bool RISCVTargetInfo::validateCpuIs(StringRef CPUName) const {
513+
llvm::Triple Triple = getTriple();
514+
assert(Triple.isOSLinux() &&
515+
"__builtin_cpu_is() is only supported for Linux.");
516+
517+
return llvm::RISCV::hasValidCPUModel(CPUName);
518+
}

‎clang/lib/Basic/Targets/RISCV.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -128,8 +128,10 @@ class RISCVTargetInfo : public TargetInfo {
128128
}
129129

130130
bool supportsCpuSupports() const override { return getTriple().isOSLinux(); }
131+
bool supportsCpuIs() const override { return getTriple().isOSLinux(); }
131132
bool supportsCpuInit() const override { return getTriple().isOSLinux(); }
132133
bool validateCpuSupports(StringRef Feature) const override;
134+
bool validateCpuIs(StringRef CPUName) const override;
133135
bool isValidFeatureName(StringRef Name) const override;
134136

135137
bool validateGlobalRegisterVariable(StringRef RegName, unsigned RegSize,

‎clang/lib/CodeGen/CGBuiltin.cpp‎

Lines changed: 54 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -67,6 +67,7 @@
6767
#include "llvm/Support/ScopedPrinter.h"
6868
#include "llvm/TargetParser/AArch64TargetParser.h"
6969
#include "llvm/TargetParser/RISCVISAInfo.h"
70+
#include "llvm/TargetParser/RISCVTargetParser.h"
7071
#include "llvm/TargetParser/X86TargetParser.h"
7172
#include <optional>
7273
#include <sstream>
@@ -22505,6 +22506,57 @@ Value *CodeGenFunction::EmitHexagonBuiltinExpr(unsigned BuiltinID,
2250522506
return nullptr;
2250622507
}
2250722508

22509+
Value *CodeGenFunction::EmitRISCVCpuIs(const CallExpr *E) {
22510+
const Expr *CPUExpr = E->getArg(0)->IgnoreParenCasts();
22511+
StringRef CPUStr = cast<clang::StringLiteral>(CPUExpr)->getString();
22512+
return EmitRISCVCpuIs(CPUStr);
22513+
}
22514+
22515+
Value *CodeGenFunction::EmitRISCVCpuIs(StringRef CPUStr) {
22516+
llvm::Type *Int32Ty = Builder.getInt32Ty();
22517+
llvm::Type *Int64Ty = Builder.getInt64Ty();
22518+
llvm::Type *MXLenType =
22519+
CGM.getTarget().getTriple().isArch32Bit() ? Int32Ty : Int64Ty;
22520+
22521+
llvm::Type *StructTy = llvm::StructType::get(Int32Ty, MXLenType, MXLenType);
22522+
llvm::Constant *RISCVCPUModel =
22523+
CGM.CreateRuntimeVariable(StructTy, "__riscv_cpu_model");
22524+
cast<llvm::GlobalValue>(RISCVCPUModel)->setDSOLocal(true);
22525+
22526+
auto loadRISCVCPUID = [&](unsigned Index, llvm::Type *ValueTy,
22527+
CGBuilderTy &Builder, CodeGenModule &CGM) {
22528+
llvm::Value *GEPIndices[] = {Builder.getInt32(0),
22529+
llvm::ConstantInt::get(Int32Ty, Index)};
22530+
Value *Ptr = Builder.CreateInBoundsGEP(StructTy, RISCVCPUModel, GEPIndices);
22531+
Value *CPUID = Builder.CreateAlignedLoad(
22532+
ValueTy, Ptr,
22533+
CharUnits::fromQuantity(ValueTy->getScalarSizeInBits() / 8));
22534+
return CPUID;
22535+
};
22536+
22537+
// Compare mvendorid.
22538+
Value *VendorID = loadRISCVCPUID(0, Int32Ty, Builder, CGM);
22539+
Value *Result = Builder.CreateICmpEQ(
22540+
VendorID,
22541+
llvm::ConstantInt::get(Int32Ty, llvm::RISCV::getVendorID(CPUStr)));
22542+
22543+
// Compare marchid.
22544+
Value *ArchID = loadRISCVCPUID(1, MXLenType, Builder, CGM);
22545+
Result = Builder.CreateAnd(
22546+
Result, Builder.CreateICmpEQ(
22547+
ArchID, llvm::ConstantInt::get(
22548+
MXLenType, llvm::RISCV::getArchID(CPUStr))));
22549+
22550+
// Compare mimplid.
22551+
Value *ImplID = loadRISCVCPUID(2, MXLenType, Builder, CGM);
22552+
Result = Builder.CreateAnd(
22553+
Result, Builder.CreateICmpEQ(
22554+
ImplID, llvm::ConstantInt::get(
22555+
MXLenType, llvm::RISCV::getImplID(CPUStr))));
22556+
22557+
return Result;
22558+
}
22559+
2250822560
Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
2250922561
const CallExpr *E,
2251022562
ReturnValueSlot ReturnValue) {
@@ -22513,6 +22565,8 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
2251322565
return EmitRISCVCpuSupports(E);
2251422566
if (BuiltinID == Builtin::BI__builtin_cpu_init)
2251522567
return EmitRISCVCpuInit();
22568+
if (BuiltinID == Builtin::BI__builtin_cpu_is)
22569+
return EmitRISCVCpuIs(E);
2251622570

2251722571
SmallVector<Value *, 4> Ops;
2251822572
llvm::Type *ResultType = ConvertType(E->getType());

‎clang/lib/CodeGen/CodeGenFunction.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4730,6 +4730,8 @@ class CodeGenFunction : public CodeGenTypeCache {
47304730
llvm::Value *EmitRISCVCpuSupports(const CallExpr *E);
47314731
llvm::Value *EmitRISCVCpuSupports(ArrayRef<StringRef> FeaturesStrs);
47324732
llvm::Value *EmitRISCVCpuInit();
4733+
llvm::Value *EmitRISCVCpuIs(const CallExpr *E);
4734+
llvm::Value *EmitRISCVCpuIs(StringRef CPUStr);
47334735

47344736
void AddAMDGPUFenceAddressSpaceMMRA(llvm::Instruction *Inst,
47354737
const CallExpr *E);

‎clang/test/CodeGen/builtin-cpu-is.c‎

Lines changed: 110 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,26 @@
1-
// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -emit-llvm < %s| FileCheck %s
1+
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5
2+
// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK-X86
3+
// RUN: %clang_cc1 -triple riscv64-unknown-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK-RV64
24

5+
#ifdef __x86_64__
36
// Test that we have the structure definition, the gep offsets, the name of the
47
// global, the bit grab, and the icmp correct.
58
extern void a(const char *);
69

710
// CHECK: @__cpu_model = external dso_local global { i32, i32, i32, [1 x i32] }
811

12+
// CHECK-X86-LABEL: define dso_local void @intel(
13+
// CHECK-X86-SAME: ) #[[ATTR0:[0-9]+]] {
14+
// CHECK-X86-NEXT: [[ENTRY:.*:]]
15+
// CHECK-X86-NEXT: [[TMP0:%.*]] = load i32, ptr @__cpu_model, align 4
16+
// CHECK-X86-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP0]], 1
17+
// CHECK-X86-NEXT: br i1 [[TMP1]], label %[[IF_THEN:.*]], label %[[IF_END:.*]]
18+
// CHECK-X86: [[IF_THEN]]:
19+
// CHECK-X86-NEXT: call void @a(ptr noundef @.str)
20+
// CHECK-X86-NEXT: br label %[[IF_END]]
21+
// CHECK-X86: [[IF_END]]:
22+
// CHECK-X86-NEXT: ret void
23+
//
924
void intel(void) {
1025
if (__builtin_cpu_is("intel"))
1126
a("intel");
@@ -14,6 +29,18 @@ void intel(void) {
1429
// CHECK: = icmp eq i32 [[LOAD]], 1
1530
}
1631

32+
// CHECK-X86-LABEL: define dso_local void @amd(
33+
// CHECK-X86-SAME: ) #[[ATTR0]] {
34+
// CHECK-X86-NEXT: [[ENTRY:.*:]]
35+
// CHECK-X86-NEXT: [[TMP0:%.*]] = load i32, ptr @__cpu_model, align 4
36+
// CHECK-X86-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP0]], 2
37+
// CHECK-X86-NEXT: br i1 [[TMP1]], label %[[IF_THEN:.*]], label %[[IF_END:.*]]
38+
// CHECK-X86: [[IF_THEN]]:
39+
// CHECK-X86-NEXT: call void @a(ptr noundef @.str.1)
40+
// CHECK-X86-NEXT: br label %[[IF_END]]
41+
// CHECK-X86: [[IF_END]]:
42+
// CHECK-X86-NEXT: ret void
43+
//
1744
void amd(void) {
1845
if (__builtin_cpu_is("amd"))
1946
a("amd");
@@ -22,6 +49,18 @@ void amd(void) {
2249
// CHECK: = icmp eq i32 [[LOAD]], 2
2350
}
2451

52+
// CHECK-X86-LABEL: define dso_local void @atom(
53+
// CHECK-X86-SAME: ) #[[ATTR0]] {
54+
// CHECK-X86-NEXT: [[ENTRY:.*:]]
55+
// CHECK-X86-NEXT: [[TMP0:%.*]] = load i32, ptr getelementptr inbounds ({ i32, i32, i32, [1 x i32] }, ptr @__cpu_model, i32 0, i32 1), align 4
56+
// CHECK-X86-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP0]], 1
57+
// CHECK-X86-NEXT: br i1 [[TMP1]], label %[[IF_THEN:.*]], label %[[IF_END:.*]]
58+
// CHECK-X86: [[IF_THEN]]:
59+
// CHECK-X86-NEXT: call void @a(ptr noundef @.str.2)
60+
// CHECK-X86-NEXT: br label %[[IF_END]]
61+
// CHECK-X86: [[IF_END]]:
62+
// CHECK-X86-NEXT: ret void
63+
//
2564
void atom(void) {
2665
if (__builtin_cpu_is("atom"))
2766
a("atom");
@@ -30,6 +69,18 @@ void atom(void) {
3069
// CHECK: = icmp eq i32 [[LOAD]], 1
3170
}
3271

72+
// CHECK-X86-LABEL: define dso_local void @amdfam10h(
73+
// CHECK-X86-SAME: ) #[[ATTR0]] {
74+
// CHECK-X86-NEXT: [[ENTRY:.*:]]
75+
// CHECK-X86-NEXT: [[TMP0:%.*]] = load i32, ptr getelementptr inbounds ({ i32, i32, i32, [1 x i32] }, ptr @__cpu_model, i32 0, i32 1), align 4
76+
// CHECK-X86-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP0]], 4
77+
// CHECK-X86-NEXT: br i1 [[TMP1]], label %[[IF_THEN:.*]], label %[[IF_END:.*]]
78+
// CHECK-X86: [[IF_THEN]]:
79+
// CHECK-X86-NEXT: call void @a(ptr noundef @.str.3)
80+
// CHECK-X86-NEXT: br label %[[IF_END]]
81+
// CHECK-X86: [[IF_END]]:
82+
// CHECK-X86-NEXT: ret void
83+
//
3384
void amdfam10h(void) {
3485
if (__builtin_cpu_is("amdfam10h"))
3586
a("amdfam10h");
@@ -38,6 +89,18 @@ void amdfam10h(void) {
3889
// CHECK: = icmp eq i32 [[LOAD]], 4
3990
}
4091

92+
// CHECK-X86-LABEL: define dso_local void @barcelona(
93+
// CHECK-X86-SAME: ) #[[ATTR0]] {
94+
// CHECK-X86-NEXT: [[ENTRY:.*:]]
95+
// CHECK-X86-NEXT: [[TMP0:%.*]] = load i32, ptr getelementptr inbounds ({ i32, i32, i32, [1 x i32] }, ptr @__cpu_model, i32 0, i32 2), align 4
96+
// CHECK-X86-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP0]], 4
97+
// CHECK-X86-NEXT: br i1 [[TMP1]], label %[[IF_THEN:.*]], label %[[IF_END:.*]]
98+
// CHECK-X86: [[IF_THEN]]:
99+
// CHECK-X86-NEXT: call void @a(ptr noundef @.str.4)
100+
// CHECK-X86-NEXT: br label %[[IF_END]]
101+
// CHECK-X86: [[IF_END]]:
102+
// CHECK-X86-NEXT: ret void
103+
//
41104
void barcelona(void) {
42105
if (__builtin_cpu_is("barcelona"))
43106
a("barcelona");
@@ -46,10 +109,56 @@ void barcelona(void) {
46109
// CHECK: = icmp eq i32 [[LOAD]], 4
47110
}
48111

112+
// CHECK-X86-LABEL: define dso_local void @nehalem(
113+
// CHECK-X86-SAME: ) #[[ATTR0]] {
114+
// CHECK-X86-NEXT: [[ENTRY:.*:]]
115+
// CHECK-X86-NEXT: [[TMP0:%.*]] = load i32, ptr getelementptr inbounds ({ i32, i32, i32, [1 x i32] }, ptr @__cpu_model, i32 0, i32 2), align 4
116+
// CHECK-X86-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP0]], 1
117+
// CHECK-X86-NEXT: br i1 [[TMP1]], label %[[IF_THEN:.*]], label %[[IF_END:.*]]
118+
// CHECK-X86: [[IF_THEN]]:
119+
// CHECK-X86-NEXT: call void @a(ptr noundef @.str.5)
120+
// CHECK-X86-NEXT: br label %[[IF_END]]
121+
// CHECK-X86: [[IF_END]]:
122+
// CHECK-X86-NEXT: ret void
123+
//
49124
void nehalem(void) {
50125
if (__builtin_cpu_is("nehalem"))
51126
a("nehalem");
52127

53128
// CHECK: [[LOAD:%[^ ]+]] = load i32, ptr getelementptr inbounds ({ i32, i32, i32, [1 x i32] }, ptr @__cpu_model, i32 0, i32 2)
54129
// CHECK: = icmp eq i32 [[LOAD]], 1
55130
}
131+
#endif
132+
133+
#ifdef __riscv
134+
// CHECK-RV64-LABEL: define dso_local signext i32 @test_riscv(
135+
// CHECK-RV64-SAME: i32 noundef signext [[A:%.*]]) #[[ATTR0:[0-9]+]] {
136+
// CHECK-RV64-NEXT: [[ENTRY:.*:]]
137+
// CHECK-RV64-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
138+
// CHECK-RV64-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
139+
// CHECK-RV64-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
140+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = load i32, ptr @__riscv_cpu_model, align 4
141+
// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP0]], 1567
142+
// CHECK-RV64-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, i64, i64 }, ptr @__riscv_cpu_model, i32 0, i32 1), align 8
143+
// CHECK-RV64-NEXT: [[TMP3:%.*]] = icmp eq i64 [[TMP2]], -9223372036854710272
144+
// CHECK-RV64-NEXT: [[TMP4:%.*]] = and i1 [[TMP1]], [[TMP3]]
145+
// CHECK-RV64-NEXT: [[TMP5:%.*]] = load i64, ptr getelementptr inbounds ({ i32, i64, i64 }, ptr @__riscv_cpu_model, i32 0, i32 2), align 8
146+
// CHECK-RV64-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 273
147+
// CHECK-RV64-NEXT: [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP6]]
148+
// CHECK-RV64-NEXT: br i1 [[TMP7]], label %[[IF_THEN:.*]], label %[[IF_END:.*]]
149+
// CHECK-RV64: [[IF_THEN]]:
150+
// CHECK-RV64-NEXT: store i32 3, ptr [[RETVAL]], align 4
151+
// CHECK-RV64-NEXT: br label %[[RETURN:.*]]
152+
// CHECK-RV64: [[IF_END]]:
153+
// CHECK-RV64-NEXT: store i32 0, ptr [[RETVAL]], align 4
154+
// CHECK-RV64-NEXT: br label %[[RETURN]]
155+
// CHECK-RV64: [[RETURN]]:
156+
// CHECK-RV64-NEXT: [[TMP8:%.*]] = load i32, ptr [[RETVAL]], align 4
157+
// CHECK-RV64-NEXT: ret i32 [[TMP8]]
158+
//
159+
int test_riscv(int a) {
160+
if (__builtin_cpu_is("veyron-v1"))
161+
return 3;
162+
return 0;
163+
}
164+
#endif

‎llvm/include/llvm/TargetParser/RISCVTargetParser.h‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -45,6 +45,10 @@ void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64);
4545
void fillValidTuneCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64);
4646
bool hasFastScalarUnalignedAccess(StringRef CPU);
4747
bool hasFastVectorUnalignedAccess(StringRef CPU);
48+
bool hasValidCPUModel(StringRef CPU);
49+
uint32_t getVendorID(StringRef CPU);
50+
uint64_t getArchID(StringRef CPU);
51+
uint64_t getImplID(StringRef CPU);
4852

4953
} // namespace RISCV
5054

‎llvm/lib/Target/RISCV/RISCVProcessors.td‎

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -49,6 +49,9 @@ class RISCVProcessorModel<string n,
4949
string default_march = "">
5050
: ProcessorModel<n, m, f, tunef> {
5151
string DefaultMarch = default_march;
52+
int MVendorID = 0;
53+
int MArchID = 0;
54+
int MImpID = 0;
5255
}
5356

5457
class RISCVTuneProcessorModel<string n,
@@ -435,7 +438,11 @@ def VENTANA_VEYRON_V1 : RISCVProcessorModel<"veyron-v1",
435438
TuneZExtHFusion,
436439
TuneZExtWFusion,
437440
TuneShiftedZExtWFusion,
438-
TuneLDADDFusion]>;
441+
TuneLDADDFusion]> {
442+
let MVendorID = 0x61f;
443+
let MArchID = 0x8000000000010000;
444+
let MImpID = 0x111;
445+
}
439446

440447
def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
441448
XiangShanNanHuModel,

‎llvm/lib/TargetParser/RISCVTargetParser.cpp‎

Lines changed: 40 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,7 @@ namespace RISCV {
2222

2323
enum CPUKind : unsigned {
2424
#define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN, \
25-
FAST_VECTOR_UNALIGN) \
25+
FAST_VECTOR_UNALIGN, MVENDORID, MARCHID, MIMPID) \
2626
CK_##ENUM,
2727
#define TUNE_PROC(ENUM, NAME) CK_##ENUM,
2828
#include "llvm/TargetParser/RISCVTargetParserDef.inc"
@@ -33,13 +33,24 @@ struct CPUInfo {
3333
StringLiteral DefaultMarch;
3434
bool FastScalarUnalignedAccess;
3535
bool FastVectorUnalignedAccess;
36+
uint32_t MVendorID;
37+
uint64_t MArchID;
38+
uint64_t MImpID;
3639
bool is64Bit() const { return DefaultMarch.starts_with("rv64"); }
3740
};
3841

3942
constexpr CPUInfo RISCVCPUInfo[] = {
4043
#define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN, \
41-
FAST_VECTOR_UNALIGN) \
42-
{NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN, FAST_VECTOR_UNALIGN},
44+
FAST_VECTOR_UNALIGN, MVENDORID, MARCHID, MIMPID) \
45+
{ \
46+
NAME, \
47+
DEFAULT_MARCH, \
48+
FAST_SCALAR_UNALIGN, \
49+
FAST_VECTOR_UNALIGN, \
50+
MVENDORID, \
51+
MARCHID, \
52+
MIMPID, \
53+
},
4354
#include "llvm/TargetParser/RISCVTargetParserDef.inc"
4455
};
4556

@@ -60,6 +71,32 @@ bool hasFastVectorUnalignedAccess(StringRef CPU) {
6071
return Info && Info->FastVectorUnalignedAccess;
6172
}
6273

74+
bool hasValidCPUModel(StringRef CPU) {
75+
const CPUInfo *Info = getCPUInfoByName(CPU);
76+
return Info && Info->MVendorID && Info->MArchID && Info->MImpID;
77+
}
78+
79+
uint32_t getVendorID(StringRef CPU) {
80+
const CPUInfo *Info = getCPUInfoByName(CPU);
81+
if (!Info)
82+
return false;
83+
return Info->MVendorID;
84+
}
85+
86+
uint64_t getArchID(StringRef CPU) {
87+
const CPUInfo *Info = getCPUInfoByName(CPU);
88+
if (!Info)
89+
return false;
90+
return Info->MArchID;
91+
}
92+
93+
uint64_t getImplID(StringRef CPU) {
94+
const CPUInfo *Info = getCPUInfoByName(CPU);
95+
if (!Info)
96+
return false;
97+
return Info->MImpID;
98+
}
99+
63100
bool parseCPU(StringRef CPU, bool IsRV64) {
64101
const CPUInfo *Info = getCPUInfoByName(CPU);
65102

‎llvm/test/TableGen/riscv-target-def.td‎

Lines changed: 8 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -81,6 +81,9 @@ class RISCVProcessorModel<string n,
8181
string default_march = "">
8282
: ProcessorModel<n, m, f, tunef> {
8383
string DefaultMarch = default_march;
84+
int MVendorID = 0;
85+
int MArchID = 0;
86+
int MImpID = 0;
8487
}
8588

8689
class RISCVTuneProcessorModel<string n,
@@ -160,13 +163,13 @@ def ROCKET : RISCVTuneProcessorModel<"rocket",
160163
// CHECK: #endif // GET_SUPPORTED_PROFILES
161164

162165
// CHECK: #ifndef PROC
163-
// CHECK-NEXT: #define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN, FAST_VECTOR_UNALIGN)
166+
// CHECK-NEXT: #define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN, FAST_VECTOR_UNALIGN, MVENDORID, MARCHID, MIMPID)
164167
// CHECK-NEXT: #endif
165168

166-
// CHECK: PROC(GENERIC_RV32, {"generic-rv32"}, {"rv32i2p1"}, 0, 0)
167-
// CHECK-NEXT: PROC(GENERIC_RV64, {"generic-rv64"}, {"rv64i2p1"}, 0, 0)
168-
// CHECK-NEXT: PROC(ROCKET_RV32, {"rocket-rv32"}, {"rv32i2p1_zicsr2p0_zidummy0p1_zifencei2p0"}, 0, 0)
169-
// CHECK-NEXT: PROC(ROCKET_RV64, {"rocket-rv64"}, {"rv64i2p1_zicsr2p0_zidummy0p1_zifencei2p0"}, 0, 0)
169+
// CHECK: PROC(GENERIC_RV32, {"generic-rv32"}, {"rv32i2p1"}, 0, 0, 0x00000000, 0x00000000, 0x00000000)
170+
// CHECK-NEXT: PROC(GENERIC_RV64, {"generic-rv64"}, {"rv64i2p1"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
171+
// CHECK-NEXT: PROC(ROCKET_RV32, {"rocket-rv32"}, {"rv32i2p1_zicsr2p0_zidummy0p1_zifencei2p0"}, 0, 0, 0x00000000, 0x00000000, 0x00000000)
172+
// CHECK-NEXT: PROC(ROCKET_RV64, {"rocket-rv64"}, {"rv64i2p1_zicsr2p0_zidummy0p1_zifencei2p0"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
170173

171174
// CHECK: #undef PROC
172175

0 commit comments

Comments
 (0)