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[RISCV] Add OperandType for vector rounding mode operands.
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4 files changed

+27
-14
lines changed

4 files changed

+27
-14
lines changed

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -341,7 +341,9 @@ enum OperandType : unsigned {
341341
OPERAND_VEC_POLICY,
342342
// Vector SEW operand.
343343
OPERAND_SEW,
344-
OPERAND_LAST_RISCV_IMM = OPERAND_SEW,
344+
// Vector rounding mode for VXRM or FRM.
345+
OPERAND_VEC_RM,
346+
OPERAND_LAST_RISCV_IMM = OPERAND_VEC_RM,
345347
// Operand is either a register or uimm5, this is used by V extension pseudo
346348
// instructions to represent a value that be passed as AVL to either vsetvli
347349
// or vsetivli.

‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp‎

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2551,6 +2551,13 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
25512551
case RISCVOp::OPERAND_SEW:
25522552
Ok = Imm == 0 || (Imm >= 3 && Imm <= 6);
25532553
break;
2554+
case RISCVOp::OPERAND_VEC_RM:
2555+
assert(RISCVII::hasRoundModeOp(Desc.TSFlags));
2556+
if (RISCVII::usesVXRM(Desc.TSFlags))
2557+
Ok = isUInt<2>(Imm);
2558+
else
2559+
Ok = RISCVFPRndMode::isValidRoundingMode(Imm);
2560+
break;
25542561
}
25552562
if (!Ok) {
25562563
ErrInfo = "Invalid immediate";

‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td‎

Lines changed: 14 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -92,6 +92,10 @@ def sew : RISCVOp {
9292
let OperandType = "OPERAND_SEW";
9393
}
9494

95+
def vec_rm : RISCVOp {
96+
let OperandType = "OPERAND_VEC_RM";
97+
}
98+
9599
// X0 has special meaning for vsetvl/vsetvli.
96100
// rd | rs1 | AVL value | Effect on vl
97101
//--------------------------------------------------------------
@@ -1057,7 +1061,7 @@ class VPseudoUnaryNoMaskRoundingMode<DAGOperand RetClass,
10571061
string Constraint = "",
10581062
int TargetConstraintType = 1> :
10591063
Pseudo<(outs RetClass:$rd),
1060-
(ins RetClass:$passthru, OpClass:$rs2, ixlenimm:$rm,
1064+
(ins RetClass:$passthru, OpClass:$rs2, vec_rm:$rm,
10611065
AVL:$vl, sew:$sew, vec_policy:$policy), []>,
10621066
RISCVVPseudo {
10631067
let mayLoad = 0;
@@ -1097,7 +1101,7 @@ class VPseudoUnaryMaskRoundingMode<VReg RetClass,
10971101
int TargetConstraintType = 1> :
10981102
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
10991103
(ins GetVRegNoV0<RetClass>.R:$passthru, OpClass:$rs2,
1100-
VMaskOp:$vm, ixlenimm:$rm,
1104+
VMaskOp:$vm, vec_rm:$rm,
11011105
AVL:$vl, sew:$sew, vec_policy:$policy), []>,
11021106
RISCVVPseudo {
11031107
let mayLoad = 0;
@@ -1135,7 +1139,7 @@ class VPseudoUnaryNoMask_FRM<VReg RetClass,
11351139
string Constraint = "",
11361140
int TargetConstraintType = 1> :
11371141
Pseudo<(outs RetClass:$rd),
1138-
(ins RetClass:$passthru, OpClass:$rs2, ixlenimm:$frm,
1142+
(ins RetClass:$passthru, OpClass:$rs2, vec_rm:$frm,
11391143
AVL:$vl, sew:$sew, vec_policy:$policy), []>,
11401144
RISCVVPseudo {
11411145
let mayLoad = 0;
@@ -1155,7 +1159,7 @@ class VPseudoUnaryMask_FRM<VReg RetClass,
11551159
int TargetConstraintType = 1> :
11561160
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
11571161
(ins GetVRegNoV0<RetClass>.R:$passthru, OpClass:$rs2,
1158-
VMaskOp:$vm, ixlenimm:$frm,
1162+
VMaskOp:$vm, vec_rm:$frm,
11591163
AVL:$vl, sew:$sew, vec_policy:$policy), []>,
11601164
RISCVVPseudo {
11611165
let mayLoad = 0;
@@ -1250,7 +1254,7 @@ class VPseudoBinaryNoMaskRoundingMode<VReg RetClass,
12501254
int UsesVXRM_ = 1,
12511255
int TargetConstraintType = 1> :
12521256
Pseudo<(outs RetClass:$rd),
1253-
(ins RetClass:$passthru, Op1Class:$rs2, Op2Class:$rs1, ixlenimm:$rm,
1257+
(ins RetClass:$passthru, Op1Class:$rs2, Op2Class:$rs1, vec_rm:$rm,
12541258
AVL:$vl, sew:$sew, vec_policy:$policy), []>,
12551259
RISCVVPseudo {
12561260
let mayLoad = 0;
@@ -1273,7 +1277,7 @@ class VPseudoBinaryMaskPolicyRoundingMode<VReg RetClass,
12731277
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
12741278
(ins GetVRegNoV0<RetClass>.R:$passthru,
12751279
Op1Class:$rs2, Op2Class:$rs1,
1276-
VMaskOp:$vm, ixlenimm:$rm, AVL:$vl,
1280+
VMaskOp:$vm, vec_rm:$rm, AVL:$vl,
12771281
sew:$sew, vec_policy:$policy), []>,
12781282
RISCVVPseudo {
12791283
let mayLoad = 0;
@@ -1317,7 +1321,7 @@ class VPseudoTiedBinaryNoMaskRoundingMode<VReg RetClass,
13171321
int TargetConstraintType = 1> :
13181322
Pseudo<(outs RetClass:$rd),
13191323
(ins RetClass:$rs2, Op2Class:$rs1,
1320-
ixlenimm:$rm,
1324+
vec_rm:$rm,
13211325
AVL:$vl, sew:$sew,
13221326
vec_policy:$policy), []>,
13231327
RISCVVPseudo {
@@ -1408,7 +1412,7 @@ class VPseudoTernaryMaskPolicyRoundingMode<VReg RetClass,
14081412
(ins GetVRegNoV0<RetClass>.R:$passthru,
14091413
Op1Class:$rs2, Op2Class:$rs1,
14101414
VMaskOp:$vm,
1411-
ixlenimm:$rm,
1415+
vec_rm:$rm,
14121416
AVL:$vl, sew:$sew, vec_policy:$policy), []>,
14131417
RISCVVPseudo {
14141418
let mayLoad = 0;
@@ -1475,7 +1479,7 @@ class VPseudoTiedBinaryMaskRoundingMode<VReg RetClass,
14751479
(ins GetVRegNoV0<RetClass>.R:$passthru,
14761480
Op2Class:$rs1,
14771481
VMaskOp:$vm,
1478-
ixlenimm:$rm,
1482+
vec_rm:$rm,
14791483
AVL:$vl, sew:$sew, vec_policy:$policy), []>,
14801484
RISCVVPseudo {
14811485
let mayLoad = 0;
@@ -1578,7 +1582,7 @@ class VPseudoTernaryNoMaskWithPolicyRoundingMode<VReg RetClass,
15781582
int TargetConstraintType = 1> :
15791583
Pseudo<(outs RetClass:$rd),
15801584
(ins RetClass:$rs3, Op1Class:$rs1, Op2Class:$rs2,
1581-
ixlenimm:$rm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
1585+
vec_rm:$rm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
15821586
RISCVVPseudo {
15831587
let mayLoad = 0;
15841588
let mayStore = 0;

‎llvm/test/CodeGen/RISCV/rvv/frm-insert.ll‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -559,7 +559,7 @@ define <vscale x 1 x float> @after_fsrm3(<vscale x 1 x float> %0, <vscale x 1 x
559559
; CHECK-LABEL: after_fsrm3:
560560
; CHECK: # %bb.0: # %entry
561561
; CHECK-NEXT: fsrmi 4
562-
; CHECK-NEXT: fsrmi a1, 5
562+
; CHECK-NEXT: fsrmi a1, 3
563563
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
564564
; CHECK-NEXT: vfadd.vv v8, v8, v9
565565
; CHECK-NEXT: fsrm a1
@@ -568,7 +568,7 @@ define <vscale x 1 x float> @after_fsrm3(<vscale x 1 x float> %0, <vscale x 1 x
568568
; UNOPT-LABEL: after_fsrm3:
569569
; UNOPT: # %bb.0: # %entry
570570
; UNOPT-NEXT: fsrmi 4
571-
; UNOPT-NEXT: fsrmi a1, 5
571+
; UNOPT-NEXT: fsrmi a1, 3
572572
; UNOPT-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
573573
; UNOPT-NEXT: vfadd.vv v8, v8, v9
574574
; UNOPT-NEXT: fsrm a1
@@ -579,7 +579,7 @@ entry:
579579
<vscale x 1 x float> undef,
580580
<vscale x 1 x float> %0,
581581
<vscale x 1 x float> %1,
582-
i64 5, i64 %2)
582+
i64 3, i64 %2)
583583
ret <vscale x 1 x float> %a
584584
}
585585

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