llvm: fix few typos in filecheck tests

klensy · klensy · commit fbc3212e3c18 · 2024-05-23T16:44:08.000+03:00
and few more
diff --git a/llvm/test/Analysis/CostModel/AArch64/sve-shuffle-broadcast.ll b/llvm/test/Analysis/CostModel/AArch64/sve-shuffle-broadcast.ll
@@ -31,7 +31,7 @@ define void  @broadcast() #0{
 ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction:   %22 = shufflevector <vscale x 8 x i1> undef, <vscale x 8 x i1> undef, <vscale x 8 x i32> zeroinitializer
 ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction:   %23 = shufflevector <vscale x 4 x i1> undef, <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
 ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction:   %24 = shufflevector <vscale x 2 x i1> undef, <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer
-; CHECK-NETX: Cost Model: Found an estimated cost of 0 for instruction:   ret void
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction:   ret void
 
   %zero = shufflevector <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
   %1 = shufflevector <vscale x 32 x i8> undef, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
diff --git a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/diverged-entry-headers.ll b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/diverged-entry-headers.ll
@@ -90,7 +90,7 @@ S:
   br i1 %cond.uni, label %exit, label %T
 
 T:
-; CHECK-NIT:   DIVERGENT:   %tt.phi = phi i32
+; CHECK-NOT:   DIVERGENT:   %tt.phi = phi i32
   %tt.phi = phi i32 [ %ss, %S ], [ %a, %entry ]
   %tt = add i32 %b, 1
   br label %P
diff --git a/llvm/test/CodeGen/AArch64/arm64_32-atomics.ll b/llvm/test/CodeGen/AArch64/arm64_32-atomics.ll
@@ -2,70 +2,70 @@
 ; RUN: llc -mtriple=arm64_32-apple-ios7.0 -mattr=+outline-atomics -o - %s | FileCheck %s -check-prefix=OUTLINE-ATOMICS
 
 define i8 @test_load_8(ptr %addr) {
-; CHECK-LABAL: test_load_8:
+; CHECK-LABEL: test_load_8:
 ; CHECK: ldarb w0, [x0]
   %val = load atomic i8, ptr %addr seq_cst, align 1
   ret i8 %val
 }
 
 define i16 @test_load_16(ptr %addr) {
-; CHECK-LABAL: test_load_16:
+; CHECK-LABEL: test_load_16:
 ; CHECK: ldarh w0, [x0]
   %val = load atomic i16, ptr %addr acquire, align 2
   ret i16 %val
 }
 
 define i32 @test_load_32(ptr %addr) {
-; CHECK-LABAL: test_load_32:
+; CHECK-LABEL: test_load_32:
 ; CHECK: ldar w0, [x0]
   %val = load atomic i32, ptr %addr seq_cst, align 4
   ret i32 %val
 }
 
 define i64 @test_load_64(ptr %addr) {
-; CHECK-LABAL: test_load_64:
+; CHECK-LABEL: test_load_64:
 ; CHECK: ldar x0, [x0]
   %val = load atomic i64, ptr %addr seq_cst, align 8
   ret i64 %val
 }
 
 define ptr @test_load_ptr(ptr %addr) {
-; CHECK-LABAL: test_load_ptr:
+; CHECK-LABEL: test_load_ptr:
 ; CHECK: ldar w0, [x0]
   %val = load atomic ptr, ptr %addr seq_cst, align 8
   ret ptr %val
 }
 
 define void @test_store_8(ptr %addr) {
-; CHECK-LABAL: test_store_8:
+; CHECK-LABEL: test_store_8:
 ; CHECK: stlrb wzr, [x0]
   store atomic i8 0, ptr %addr seq_cst, align 1
   ret void
 }
 
 define void @test_store_16(ptr %addr) {
-; CHECK-LABAL: test_store_16:
+; CHECK-LABEL: test_store_16:
 ; CHECK: stlrh wzr, [x0]
   store atomic i16 0, ptr %addr seq_cst, align 2
   ret void
 }
 
 define void @test_store_32(ptr %addr) {
-; CHECK-LABAL: test_store_32:
+; CHECK-LABEL: test_store_32:
 ; CHECK: stlr wzr, [x0]
   store atomic i32 0, ptr %addr seq_cst, align 4
   ret void
 }
 
 define void @test_store_64(ptr %addr) {
-; CHECK-LABAL: test_store_64:
+; CHECK-LABEL: test_store_64:
 ; CHECK: stlr xzr, [x0]
   store atomic i64 0, ptr %addr seq_cst, align 8
   ret void
 }
 
 define void @test_store_ptr(ptr %addr) {
-; CHECK-LABAL: test_store_ptr:
+; CHECK-LABEL: test_store_ptr:
 ; CHECK: stlr wzr, [x0]
   store atomic ptr null, ptr %addr seq_cst, align 8
   ret void
diff --git a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-diff-scope-same-key.ll b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-diff-scope-same-key.ll
@@ -28,7 +28,7 @@ define void @a() "sign-return-address"="all" {
 }
 
 define void @b() "sign-return-address"="non-leaf" {
-; CHECK-LABE:      b:                                     // @b
+; CHECK-LABEL:     b:                                     // @b
 ; V8A-NOT:         hint #25
 ; V83A-NOT:        paciasp
 ; CHECK-NOT:       .cfi_negate_ra_state
diff --git a/llvm/test/CodeGen/AArch64/stp-opt-with-renaming-undef-assert.mir b/llvm/test/CodeGen/AArch64/stp-opt-with-renaming-undef-assert.mir
@@ -12,7 +12,7 @@
 
 # This test also checks that pairwise store STP is generated.
 
-# CHECK-LABLE: test
+# CHECK-LABEL: test
 # CHECK: bb.0:
 # CHECK-NEXT: liveins: $x0, $x17, $x18
 # CHECK: renamable $q13_q14_q15 = LD3Threev16b undef renamable $x17 :: (load (s384) from `ptr undef`, align 64)
diff --git a/llvm/test/CodeGen/AMDGPU/addrspacecast.ll b/llvm/test/CodeGen/AMDGPU/addrspacecast.ll
@@ -108,7 +108,7 @@ define amdgpu_kernel void @use_global_to_flat_addrspacecast(ptr addrspace(1) %pt
 }
 
 ; no-op
-; HSA-LABEl: {{^}}use_constant_to_flat_addrspacecast:
+; HSA-LABEL: {{^}}use_constant_to_flat_addrspacecast:
 ; HSA: s_load_dwordx2 s[[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]]
 ; HSA-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]]
 ; HSA-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]]
@@ -119,7 +119,7 @@ define amdgpu_kernel void @use_constant_to_flat_addrspacecast(ptr addrspace(4) %
   ret void
 }
 
-; HSA-LABEl: {{^}}use_constant_to_global_addrspacecast:
+; HSA-LABEL: {{^}}use_constant_to_global_addrspacecast:
 ; HSA: s_load_dwordx2 s[[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]]
 ; CI-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]]
 ; CI-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]]
diff --git a/llvm/test/CodeGen/ARM/dsp-loop-indexing.ll b/llvm/test/CodeGen/ARM/dsp-loop-indexing.ll
@@ -22,7 +22,7 @@
 ; CHECK-DEFAULT: ldr{{.*}}, #4]
 ; CHECK-DEFAULT: str{{.*}}, #4]
 ; CHECK-DEFAULT: ldr{{.*}}, #8]!
-; CHECK-DEAFULT: ldr{{.*}}, #8]!
+; CHECK-DEFAULT: ldr{{.*}}, #8]!
 ; CHECK-DEFAULT: str{{.*}}, #8]!
 
 ; CHECK-COMPLEX: ldr{{.*}}, #8]!
diff --git a/llvm/test/CodeGen/Mips/optimizeAndPlusShift.ll b/llvm/test/CodeGen/Mips/optimizeAndPlusShift.ll
@@ -3,11 +3,11 @@
 ; RUN: llc < %s -mtriple=mips64el-unknown-linux-gnuabi64 | FileCheck %s --check-prefixes=MIPS64
 
 define i32 @shl_32(i32 %a, i32 %b) {
-; MIPS32-LABLE:   shl_32:
+; MIPS32-LABEL:   shl_32:
 ; MIPS32:	  # %bb.0:
 ; MIPS32-NEXT:    jr	$ra
 ; MIPS32-NEXT:    sllv	$2, $4, $5
-; MIPS64-LABLE:   shl_32:
+; MIPS64-LABEL:   shl_32:
 ; MIPS64:	  # %bb.0:
 ; MIPS64-NEXT:    sll   $1, $5, 0
 ; MIPS64-NEXT:    sll   $2, $4, 0
@@ -19,11 +19,11 @@ define i32 @shl_32(i32 %a, i32 %b) {
 }
 
 define i32 @lshr_32(i32 %a, i32 %b) {
-; MIPS32-LABLE:   lshr_32:
+; MIPS32-LABEL:   lshr_32:
 ; MIPS32:	  # %bb.0:
 ; MIPS32-NEXT:    jr	$ra
 ; MIPS32-NEXT:    srlv	$2, $4, $5
-; MIPS64-LABLE:   lshr_32:
+; MIPS64-LABEL:   lshr_32:
 ; MIPS64:	  # %bb.0:
 ; MIPS64-NEXT:    sll   $1, $5, 0
 ; MIPS64-NEXT:    sll   $2, $4, 0
@@ -35,11 +35,11 @@ define i32 @lshr_32(i32 %a, i32 %b) {
 }
 
 define i32 @ashr_32(i32 %a, i32 %b) {
-; MIPS32-LABLE:   ashr_32:
+; MIPS32-LABEL:   ashr_32:
 ; MIPS32:	  # %bb.0:
 ; MIPS32-NEXT:    jr	$ra
 ; MIPS32-NEXT:    srav	$2, $4, $5
-; MIPS64-LABLE:   ashr_32:
+; MIPS64-LABEL:   ashr_32:
 ; MIPS64:	  # %bb.0:
 ; MIPS64-NEXT:    sll   $1, $5, 0
 ; MIPS64-NEXT:    sll   $2, $4, 0
@@ -51,7 +51,7 @@ define i32 @ashr_32(i32 %a, i32 %b) {
 }
 
 define i64 @shl_64(i64 %a, i64 %b) {
-; MIPS64-LABLE:   shl_64:
+; MIPS64-LABEL:   shl_64:
 ; MIPS64:	  # %bb.0:
 ; MIPS64-NEXT:    sll   $1, $5, 0
 ; MIPS64-NEXT:    jr	$ra
@@ -62,7 +62,7 @@ define i64 @shl_64(i64 %a, i64 %b) {
 }
 
 define i64 @lshr_64(i64 %a, i64 %b) {
-; MIPS64-LABLE:   lshr_64:
+; MIPS64-LABEL:   lshr_64:
 ; MIPS64:	  # %bb.0:
 ; MIPS64-NEXT:    sll   $1, $5, 0
 ; MIPS64-NEXT:    jr	$ra
@@ -73,7 +73,7 @@ define i64 @lshr_64(i64 %a, i64 %b) {
 }
 
 define i64 @ashr_64(i64 %a, i64 %b) {
-; MIPS64-LABLE:   ashr_64:
+; MIPS64-LABEL:   ashr_64:
 ; MIPS64:	  # %bb.0:
 ; MIPS64-NEXT:    sll   $1, $5, 0
 ; MIPS64-NEXT:    jr	$ra
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_usm_storage_classes/intel-usm-addrspaces.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_usm_storage_classes/intel-usm-addrspaces.ll
@@ -6,7 +6,7 @@
 ; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
 
 ; CHECK-: Capability USMStorageClassesINTEL
-; CHECK-SPIRV-WITHOUT-NO: Capability USMStorageClassesINTEL
+; CHECK-SPIRV-WITHOUT-NOT: Capability USMStorageClassesINTEL
 ; CHECK-SPIRV-EXT-DAG: %[[DevTy:[0-9]+]] = OpTypePointer DeviceOnlyINTEL %[[#]]
 ; CHECK-SPIRV-EXT-DAG: %[[HostTy:[0-9]+]] = OpTypePointer HostOnlyINTEL %[[#]]
 ; CHECK-SPIRV-DAG: %[[CrsWrkTy:[0-9]+]] = OpTypePointer CrossWorkgroup %[[#]]
diff --git a/llvm/test/CodeGen/SystemZ/prefetch-04.ll b/llvm/test/CodeGen/SystemZ/prefetch-04.ll
@@ -6,7 +6,7 @@
 ;
 ; CHECK-LABEL: for.body
 ; CHECK: call void @llvm.prefetch.p0(ptr %scevgep, i32 1, i32 3, i32 1
-; CHECK-not: call void @llvm.prefetch
+; CHECK-NOT: call void @llvm.prefetch
 
 define void @fun(ptr nocapture %Src, ptr nocapture readonly %Dst) {
 entry:
diff --git a/llvm/test/CodeGen/X86/global-sections.ll b/llvm/test/CodeGen/X86/global-sections.ll
@@ -36,8 +36,8 @@ bb5:
 }
 
 ; LINUX:     .size   F2,
-; LINUX-NEX: .cfi_endproc
-; LINUX-NEX: .section        .rodata,"a",@progbits
+; LINUX-NEXT: .cfi_endproc
+; LINUX-NEXT: .section        .rodata,"a",@progbits
 
 ; LINUX-SECTIONS: .section        .text.F2,"ax",@progbits
 ; LINUX-SECTIONS: .size   F2,
diff --git a/llvm/test/CodeGen/X86/tailregccpic.ll b/llvm/test/CodeGen/X86/tailregccpic.ll
@@ -13,12 +13,12 @@ entry:
   ret void
 }
 
-;CHECK-LABLE: tail_call_regcall:
+;CHECK-LABEL: tail_call_regcall:
 ;CHECK:       # %bb.0:
 ;CHECK-NEXT:  jmp     __regcall3__func                # TAILCALL
 ;CHECK-NEXT:  .Lfunc_end0:
 
-;CHECK-LABLE: __regcall3__func:
+;CHECK-LABEL: __regcall3__func:
 ;CHECK:       addl    $_GLOBAL_OFFSET_TABLE_+({{.*}}), %ecx
 ;CHECK-NEXT:  movl    a0@GOT(%ecx), %ecx
 ;CHECK-NEXT:  movl    %eax, (%ecx)
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_illegal_locs.mir b/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_illegal_locs.mir
@@ -43,7 +43,7 @@ debugValueSubstitutions:
 body:  |
   bb.0.entry:
     successors: %bb.1, %bb.2
-    ; CHECK-LABE: bb.0.entry:
+    ; CHECK-LABEL: bb.0.entry:
 
     $rax = MOV64ri 1, debug-instr-number 1, debug-location !17
     DBG_INSTR_REF !16, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0), debug-location !17
@@ -69,8 +69,8 @@ body:  |
     ;KILL implicit killed $eflags, debug-instr-number 4, debug-location !17
     ;DBG_INSTR_REF !16, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(4, 0), debug-location !17
     ;;; Test non-def operand
-    ;; check:      DBG_INSTR_REF {{.+}}, dbg-instr-ref(4, 0)
-    ;; check-next: DBG_VALUE_LIST {{.+}}, $noreg
+    ;; CHECK:      DBG_INSTR_REF {{.+}}, dbg-instr-ref(4, 0)
+    ;; CHECK-NEXT: DBG_VALUE_LIST {{.+}}, $noreg
 
     $noreg = MOV32ri 1, debug-instr-number 5, debug-location !17
     DBG_INSTR_REF !16, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(5, 0), debug-location !17
diff --git a/llvm/test/MC/ARM/coff-relocations.s b/llvm/test/MC/ARM/coff-relocations.s
@@ -25,7 +25,7 @@ branch24t_1:
 	bl target
 
 @ CHECK-ENCODING-LABEL: <branch24t_1>:
-@ CHECK-ENCODING-NEXR: bl {{.+}} @ imm = #0
+@ CHECK-ENCODING-NEXT: bl {{.+}} @ imm = #0
 
 	.thumb_func
 branch20t:
diff --git a/llvm/test/MC/Mips/expansion-jal-sym-pic.s b/llvm/test/MC/Mips/expansion-jal-sym-pic.s
@@ -227,12 +227,12 @@ local_label:
 # XO32-NEXT: .reloc ($tmp1), R_MIPS_JALR, weak_label
 
 # ELF-XO32:      3c 19 00 00 lui $25, 0
-# ELF-XO32-MEXT:                  R_MIPS_CALL_HI16 weak_label
-# ELF-XO32-MEXT: 03 3c c8 21 addu $25, $25, $gp
-# ELF-XO32-MEXT: 8f 39 00 00 lw $25, 0($25)
-# ELF-XO32-MEXT:                  R_MIPS_CALL_LO16 weak_label
-# ELF-XO32-MEXT: 03 20 f8 09 jalr $25
-# ELF-XO32-MEXT:                  R_MIPS_JALR weak_label
+# ELF-XO32-NEXT:                  R_MIPS_CALL_HI16 weak_label
+# ELF-XO32-NEXT: 03 3c c8 21 addu $25, $25, $gp
+# ELF-XO32-NEXT: 8f 39 00 00 lw $25, 0($25)
+# ELF-XO32-NEXT:                  R_MIPS_CALL_LO16 weak_label
+# ELF-XO32-NEXT: 03 20 f8 09 jalr $25
+# ELF-XO32-NEXT:                  R_MIPS_JALR weak_label
 
 # N32: lw  $25, %call16(weak_label)($gp) # encoding: [0x8f,0x99,A,A]
 # N32:                                   #   fixup A - offset: 0, value: %call16(weak_label), kind:   fixup_Mips_CALL16
diff --git a/llvm/test/Transforms/Inline/update_invoke_prof.ll b/llvm/test/Transforms/Inline/update_invoke_prof.ll
@@ -66,7 +66,7 @@ ret:
 ; CHECK:  invoke void @callee2(
 ; CHECK-NEXT: {{.*}} !prof ![[PROF3:[0-9]+]]
 
-; CHECK-LABL: @callee(
+; CHECK-LABEL: @callee(
 ; CHECK:  invoke void %func(
 ; CHECK-NEXT: {{.*}} !prof ![[PROF4:[0-9]+]]
 ; CHECK:  invoke void @callee1(
diff --git a/llvm/test/Transforms/InstCombine/lifetime-sanitizer.ll b/llvm/test/Transforms/InstCombine/lifetime-sanitizer.ll
@@ -56,7 +56,7 @@ entry:
 
   call void @llvm.lifetime.start.p0(i64 1, ptr %text)
   call void @llvm.lifetime.end.p0(i64 1, ptr %text)
-  ; CHECK-NO: call void @llvm.lifetime
+  ; CHECK-NOT: call void @llvm.lifetime
 
   call void @foo(ptr %text) ; Keep alloca alive
 
diff --git a/llvm/test/Transforms/LoopUnroll/peel-loop2.ll b/llvm/test/Transforms/LoopUnroll/peel-loop2.ll
@@ -32,7 +32,7 @@ for.end:
   ret void
 }
 
-; CHECK_LABEL: @funca
+; CHECK-LABEL: @funca
 
 ; Peeled iteration
 ; CHECK: %[[REG1:[0-9]+]] = load i8, ptr @Comma
diff --git a/llvm/test/Transforms/LoopVectorize/memdep.ll b/llvm/test/Transforms/LoopVectorize/memdep.ll
@@ -244,7 +244,7 @@ for.end:
 ; RIGHTVF-LABEL: @pr34283
 ; RIGHTVF: <4 x i64>
 
-; WRONGVF-LABLE: @pr34283
+; WRONGVF-LABEL: @pr34283
 ; WRONGVF-NOT: <8 x i64>
 
 @a = common local_unnamed_addr global [64 x i32] zeroinitializer, align 16
diff --git a/llvm/test/Transforms/LoopVersioning/wrapping-pointer-non-integral-addrspace.ll b/llvm/test/Transforms/LoopVersioning/wrapping-pointer-non-integral-addrspace.ll
@@ -13,7 +13,7 @@ target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128-ni:10:11:12:13"
 declare i64 @julia_steprange_last_4949()
 
 define void @"japi1_align!_9477"(ptr %arg) {
-; LV-LAVEL: L26.lver.check
+; LV-LABEL: L26.lver.check
 ; LV: [[OFMul:%[^ ]*]]  = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 4, i64 [[Step:%[^ ]*]])
 ; LV-NEXT: [[OFMulResult:%[^ ]*]] = extractvalue { i64, i1 } [[OFMul]], 0
 ; LV-NEXT: [[OFMulOverflow:%[^ ]*]] = extractvalue { i64, i1 } [[OFMul]], 1
diff --git a/llvm/test/Transforms/PartiallyInlineLibCalls/X86/good-prototype.ll b/llvm/test/Transforms/PartiallyInlineLibCalls/X86/good-prototype.ll
@@ -21,7 +21,7 @@ entry:
 
 define float @f_writeonly(float %val) {
 ; CHECK-LABEL: @f_writeonly(
-; CHECK-NEXt:    [[RES:%.*]] = tail call float @sqrtf(float [[VAL:%.*]]) #[[READNONE]]
+; CHECK-NEXT:    [[RES:%.*]] = tail call float @sqrtf(float [[VAL:%.*]]) #[[READNONE]]
   %res = tail call float @sqrtf(float %val) writeonly
   ret float %res
 }
diff --git a/llvm/test/Verifier/AMDGPU/intrinsic-immarg.ll b/llvm/test/Verifier/AMDGPU/intrinsic-immarg.ll
@@ -670,7 +670,7 @@ declare void @llvm.amdgcn.buffer.atomic.fadd.f32(float, <4 x i32>, i32, i32, i1)
 define amdgpu_cs void @test_buffer_atomic_fadd(float %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %offset, i1 %slc) {
   ; CHECK: immarg operand has non-immediate parameter
   ; CHECK-NEXT: i1 %slc
-  ; CHECK-ENXT: call void @llvm.amdgcn.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %vindex, i32 %offset, i1 %slc)
+  ; CHECK-NEXT: call void @llvm.amdgcn.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %vindex, i32 %offset, i1 %slc)
   call void @llvm.amdgcn.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %vindex, i32 %offset, i1 %slc)
   ret void
 }
diff --git a/llvm/test/tools/llvm-ar/replace-update.test b/llvm/test/tools/llvm-ar/replace-update.test
@@ -57,7 +57,7 @@
 
 # MULTIPLE-SYM:      symbolnew1
 # MULTIPLE-SYM-NEXT: symbol2
-# MULTIPLE-SYM-NEXTs: symbolnew3
+# MULTIPLE-SYM-NEXT: symbolnew3
 
 ## Replace newer members with multiple older files:
 # RUN: llvm-ar ruU %t/multiple.a %t/1.o %t/2.o

Original file line number	Diff line number	Diff line change
`@@ -28,7 +28,7 @@ define void @a() "sign-return-address"="all" {`
`28`	`28`	`}`
`29`	`29`
`30`	`30`	`define void @b() "sign-return-address"="non-leaf" {`
`31`		`-; CHECK-LABE: b: // @b`
	`31`	`+; CHECK-LABEL: b: // @b`
`32`	`32`	`; V8A-NOT: hint #25`
`33`	`33`	`; V83A-NOT: paciasp`
`34`	`34`	`; CHECK-NOT: .cfi_negate_ra_state`
Original file line number	Diff line number	Diff line change
`@@ -6,7 +6,7 @@`
`6`	`6`	`;`
`7`	`7`	`; CHECK-LABEL: for.body`
`8`	`8`	`; CHECK: call void @llvm.prefetch.p0(ptr %scevgep, i32 1, i32 3, i32 1`
`9`		`-; CHECK-not: call void @llvm.prefetch`
	`9`	`+; CHECK-NOT: call void @llvm.prefetch`
`10`	`10`
`11`	`11`	`define void @fun(ptr nocapture %Src, ptr nocapture readonly %Dst) {`
`12`	`12`	`entry:`