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‎llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmv-with-different-class.mir‎

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
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# RUN: llc %s -o - -mtriple=riscv64 -mattr=+v -run-pass=riscv-vector-peephole \
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# RUN: | FileCheck %s
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--- |
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source_filename = "reduced.ll"
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target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
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target triple = "riscv64-unknown-linux-gnu"
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define i32 @main() #0 {
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entry:
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%0 = tail call <vscale x 1 x i32> @llvm.riscv.vmv.v.v.nxv1i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer, i64 0)
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%1 = tail call <vscale x 1 x i32> @llvm.riscv.vxor.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> zeroinitializer, <vscale x 1 x i32> zeroinitializer, <vscale x 1 x i1> zeroinitializer, i64 0, i64 0)
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%2 = tail call <vscale x 1 x i64> @llvm.riscv.vwmacc.mask.nxv1i64.nxv1i32.nxv1i32.i64(<vscale x 1 x i64> zeroinitializer, <vscale x 1 x i32> %1, <vscale x 1 x i32> zeroinitializer, <vscale x 1 x i1> zeroinitializer, i64 0, i64 0)
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%3 = tail call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv8i8_3t.nxv1i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) zeroinitializer, <vscale x 1 x i64> %2, i32 0)
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call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr null, i64 0, i64 6)
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ret i32 0
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}
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declare <vscale x 1 x i32> @llvm.riscv.vmv.v.v.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64) #1
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declare <vscale x 1 x i32> @llvm.riscv.vxor.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
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declare <vscale x 1 x i64> @llvm.riscv.vwmacc.mask.nxv1i64.nxv1i32.nxv1i32.i64(<vscale x 1 x i64>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
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declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv8i8_3t.nxv1i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), <vscale x 1 x i64>, i32 immarg) #2
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declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #3
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attributes #0 = { "target-features"="+v" }
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attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) "target-features"="+v" }
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attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) "target-features"="+v" }
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attributes #3 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) "target-features"="+v" }
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...
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---
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name: main
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alignment: 4
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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hasWinCFI: false
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noPhis: false
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isSSA: true
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noVRegs: false
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hasFakeUses: false
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callsEHReturn: false
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callsUnwindInit: false
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hasEHScopes: false
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hasEHFunclets: false
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isOutlined: false
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debugInstrRef: false
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failsVerification: false
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tracksDebugUserValues: false
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registers:
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- { id: 0, class: vr, preferred-register: '', flags: [ ] }
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- { id: 1, class: vrnov0, preferred-register: '', flags: [ ] }
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- { id: 2, class: vr, preferred-register: '', flags: [ ] }
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- { id: 3, class: vrnov0, preferred-register: '', flags: [ ] }
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- { id: 4, class: vmv0, preferred-register: '', flags: [ ] }
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- { id: 5, class: vrnov0, preferred-register: '', flags: [ ] }
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- { id: 6, class: vrnov0, preferred-register: '', flags: [ ] }
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- { id: 7, class: vmv0, preferred-register: '', flags: [ ] }
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- { id: 8, class: vr, preferred-register: '', flags: [ ] }
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- { id: 9, class: vrn3m1, preferred-register: '', flags: [ ] }
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- { id: 10, class: vrn3m1, preferred-register: '', flags: [ ] }
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- { id: 11, class: vrn3m1, preferred-register: '', flags: [ ] }
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- { id: 12, class: vrn3m1, preferred-register: '', flags: [ ] }
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- { id: 13, class: vrn3m1, preferred-register: '', flags: [ ] }
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- { id: 14, class: gpr, preferred-register: '', flags: [ ] }
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liveins: []
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 1
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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functionContext: ''
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maxCallFrameSize: 4294967295
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cvBytesOfCalleeSavedRegisters: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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hasTailCall: false
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isCalleeSavedInfoValid: false
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localFrameSize: 0
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savePoint: ''
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restorePoint: ''
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fixedStack: []
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stack: []
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entry_values: []
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callSites: []
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debugValueSubstitutions: []
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constants: []
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machineFunctionInfo:
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varArgsFrameIndex: 0
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varArgsSaveSize: 0
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: main
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; CHECK: [[PseudoVMV_V_I_MF2_:%[0-9]+]]:vr = PseudoVMV_V_I_MF2 $noreg, 0, -1, 5 /* e32 */, 0 /* tu, mu */
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; CHECK-NEXT: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 -1, 0 /* e8 */
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vmv0 = COPY [[PseudoVMCLR_M_B64_]]
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; CHECK-NEXT: [[PseudoVXOR_VV_MF2_MASK:%[0-9]+]]:vrnov0 = PseudoVXOR_VV_MF2_MASK [[PseudoVMV_V_I_MF2_]], [[PseudoVMV_V_I_MF2_]], [[PseudoVMV_V_I_MF2_]], [[COPY]], 0, 5 /* e32 */, 0 /* tu, mu */
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; CHECK-NEXT: [[PseudoVMV_V_I_M1_:%[0-9]+]]:vrnov0 = PseudoVMV_V_I_M1 $noreg, 0, -1, 6 /* e64 */, 0 /* tu, mu */
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vmv0 = COPY [[PseudoVMCLR_M_B64_]]
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; CHECK-NEXT: early-clobber %6:vrnov0 = PseudoVWMACC_VV_MF2_MASK [[PseudoVMV_V_I_M1_]], killed [[PseudoVXOR_VV_MF2_MASK]], [[PseudoVMV_V_I_MF2_]], [[COPY1]], 0, 5 /* e32 */, 0 /* tu, mu */
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; CHECK-NEXT: [[PseudoVMV_V_I_M1_1:%[0-9]+]]:vr = PseudoVMV_V_I_M1 $noreg, 0, -1, 3 /* e8 */, 0 /* tu, mu */
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; CHECK-NEXT: [[DEF:%[0-9]+]]:vrn3m1 = IMPLICIT_DEF
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; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[DEF]], [[PseudoVMV_V_I_M1_1]], %subreg.sub_vrm1_0
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; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoVMV_V_I_M1_1]], %subreg.sub_vrm1_1
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; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoVMV_V_I_M1_1]], %subreg.sub_vrm1_2
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; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[INSERT_SUBREG2]], killed %6, %subreg.sub_vrm1_0
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x0
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; CHECK-NEXT: PseudoVSSEG3E64_V_M1 killed [[INSERT_SUBREG3]], [[COPY2]], 0, 6 /* e64 */ :: (store unknown-size into `ptr null`, align 8)
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; CHECK-NEXT: $x10 = COPY [[COPY2]]
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; CHECK-NEXT: PseudoRET implicit $x10
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%0:vr = PseudoVMV_V_I_MF2 $noreg, 0, -1, 5 /* e32 */, 0 /* tu, mu */
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%1:vrnov0 = PseudoVMV_V_V_MF2 $noreg, %0, 0, 5 /* e32 */, 0 /* tu, mu */
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%2:vr = PseudoVMCLR_M_B64 -1, 0 /* e8 */
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%4:vmv0 = COPY %2
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%3:vrnov0 = PseudoVXOR_VV_MF2_MASK %1, %0, %0, %4, 0, 5 /* e32 */, 0 /* tu, mu */
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%5:vrnov0 = PseudoVMV_V_I_M1 $noreg, 0, -1, 6 /* e64 */, 0 /* tu, mu */
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%7:vmv0 = COPY %2
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early-clobber %6:vrnov0 = PseudoVWMACC_VV_MF2_MASK %5, killed %3, %0, %7, 0, 5 /* e32 */, 0 /* tu, mu */
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%8:vr = PseudoVMV_V_I_M1 $noreg, 0, -1, 3 /* e8 */, 0 /* tu, mu */
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%10:vrn3m1 = IMPLICIT_DEF
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%9:vrn3m1 = INSERT_SUBREG %10, %8, %subreg.sub_vrm1_0
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%11:vrn3m1 = INSERT_SUBREG %9, %8, %subreg.sub_vrm1_1
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%12:vrn3m1 = INSERT_SUBREG %11, %8, %subreg.sub_vrm1_2
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%13:vrn3m1 = INSERT_SUBREG %12, killed %6, %subreg.sub_vrm1_0
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%14:gpr = COPY $x0
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PseudoVSSEG3E64_V_M1 killed %13, %14, 0, 6 /* e64 */ :: (store unknown-size into `ptr null`, align 8)
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$x10 = COPY %14
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PseudoRET implicit $x10
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...

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