Remove NoUnsignedWrap check

Author: phoebewang

llvm/lib/Target/X86/X86ISelLowering.cpp

@@ -53919,7 +53919,7 @@ static SDValue combineTruncate(SDNode *N, SelectionDAG &DAG,
       return DAG.getNode(X86ISD::MMX_MOVD2W, DL, MVT::i32, BCSrc);
   }
 
-  if ((N->getFlags().hasNoUnsignedWrap() || N->getFlags().hasNoSignedWrap()) &&
+  if (N->getFlags().hasNoSignedWrap() &&
       (Src.getOpcode() == ISD::LRINT || Src.getOpcode() == ISD::LLRINT) &&
       VT.getScalarType() == MVT::i32 && Src.hasOneUse())
     return DAG.getNode(ISD::LRINT, DL, VT, Src.getOperand(0));

llvm/test/CodeGen/X86/llrint-conv.ll

@@ -249,7 +249,7 @@ define i32 @combine_f64_trunc(double %x) nounwind {
 ; X64-AVX-NEXT:    retq
 entry:
   %0 = tail call i64 @llvm.llrint.f64(double %x)
-  %1 = trunc nuw i64 %0 to i32
+  %1 = trunc nsw i64 %0 to i32
   ret i32 %1
 }
 

llvm/test/CodeGen/X86/lrint-conv-i64.ll

@@ -63,16 +63,35 @@ entry:
   ret i32 %1
 }
 
-define i32 @combine_f32_trunc(float %x) {
-; SSE-LABEL: combine_f32_trunc:
+define i32 @combine_f32_nsw_trunc(float %x) {
+; SSE-LABEL: combine_f32_nsw_trunc:
 ; SSE:       # %bb.0: # %entry
 ; SSE-NEXT:    cvtss2si %xmm0, %eax
 ; SSE-NEXT:    retq
 ;
-; AVX-LABEL: combine_f32_trunc:
+; AVX-LABEL: combine_f32_nsw_trunc:
 ; AVX:       # %bb.0: # %entry
 ; AVX-NEXT:    vcvtss2si %xmm0, %eax
 ; AVX-NEXT:    retq
+entry:
+  %0 = tail call i64 @llvm.lrint.i64.f32(float %x)
+  %1 = trunc nsw i64 %0 to i32
+  ret i32 %1
+}
+
+;; Check we don't combine trunc when nuw.
+define i32 @not_combine_f32_nuw_trunc(float %x) {
+; SSE-LABEL: not_combine_f32_nuw_trunc:
+; SSE:       # %bb.0: # %entry
+; SSE-NEXT:    cvtss2si %xmm0, %rax
+; SSE-NEXT:    # kill: def $eax killed $eax killed $rax
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: not_combine_f32_nuw_trunc:
+; AVX:       # %bb.0: # %entry
+; AVX-NEXT:    vcvtss2si %xmm0, %rax
+; AVX-NEXT:    # kill: def $eax killed $eax killed $rax
+; AVX-NEXT:    retq
 entry:
   %0 = tail call i64 @llvm.lrint.i64.f32(float %x)
   %1 = trunc nuw i64 %0 to i32
@@ -95,6 +114,22 @@ entry:
   ret i32 %1
 }
 
+;; Check "movl %eax, %eax" is present.
+define i64 @zero_upperbits_softfloat(double %x) nounwind "target-features"="+soft-float" {
+; CHECK-LABEL: zero_upperbits_softfloat:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pushq %rax
+; CHECK-NEXT:    callq lrint@PLT
+; CHECK-NEXT:    movl %eax, %eax
+; CHECK-NEXT:    popq %rcx
+; CHECK-NEXT:    retq
+entry:
+  %0 = tail call i64 @llvm.lrint.i64.f64(double %x)
+  %1 = trunc nsw i64 %0 to i32
+  %2 = zext i32 %1 to i64
+  ret i64 %2
+}
+
 declare i64 @llvm.lrint.i64.f32(float) nounwind readnone
 declare i64 @llvm.lrint.i64.f64(double) nounwind readnone
 declare i64 @llvm.lrint.i64.f80(x86_fp80) nounwind readnone

llvm/test/CodeGen/X86/vector-lrint.ll

@@ -559,6 +559,6 @@ define <4 x i32> @llrint_v4i32_v4f32(<4 x float> %x) {
 ; X64-AVX-i64-NEXT:    vcvtps2dq %xmm0, %xmm0
 ; X64-AVX-i64-NEXT:    retq
   %a = call <4 x i64> @llvm.lrint.v4i64.v4f32(<4 x float> %x)
-  %b = trunc nuw <4 x i64> %a to <4 x i32>
+  %b = trunc nsw <4 x i64> %a to <4 x i32>
   ret <4 x i32> %b
 }