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[NFC][PowerPC] Consolidate predicate definitions into PPC.td
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6 files changed

+41
-45
lines changed

6 files changed

+41
-45
lines changed

‎llvm/lib/Target/PowerPC/PPC.td‎

Lines changed: 32 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -360,7 +360,11 @@ def FeatureFastMFLR : SubtargetFeature<"fast-MFLR", "HasFastMFLR", "true",
360360

361361
//===----------------------------------------------------------------------===//
362362
// PowerPC Instruction Predicate Definitions.
363-
def In32BitMode : Predicate<"!Subtarget->isPPC64()">;
363+
364+
def IsLittleEndian : Predicate<"Subtarget->isLittleEndian()">;
365+
def IsBigEndian : Predicate<"!Subtarget->isLittleEndian()">;
366+
def IsPPC32 : Predicate<"!Subtarget->isPPC64()">;
367+
def IsPPC64 : Predicate<"Subtarget->isPPC64()">;
364368
def In64BitMode : Predicate<"Subtarget->isPPC64()">;
365369
def IsBookE : Predicate<"Subtarget->isBookE()">;
366370
def IsNotBookE : Predicate<"!Subtarget->isBookE()">;
@@ -379,20 +383,43 @@ def NaNsFPMath
379383
: Predicate<"!Subtarget->getTargetMachine().Options.NoNaNsFPMath">;
380384
def HasBPERMD : Predicate<"Subtarget->hasBPERMD()">;
381385
def HasExtDiv : Predicate<"Subtarget->hasExtDiv()">;
386+
def HasFPU : Predicate<"Subtarget->hasFPU()">;
387+
def HasHTM : Predicate<"Subtarget->hasHTM()">;
388+
def HasDirectMove : Predicate<"Subtarget->hasDirectMove()">;
389+
def HasP8Crypto : Predicate<"Subtarget->hasP8Crypto()">;
390+
def PCRelativeMemops : Predicate<"Subtarget->hasPCRelativeMemops()">;
391+
def PrefixInstrs : Predicate<"Subtarget->hasPrefixInstrs()">;
392+
def PairedVectorMemops : Predicate<"Subtarget->pairedVectorMemops()">;
393+
def MMA : Predicate<"Subtarget->hasMMA()">;
394+
395+
// Vector support predicates
396+
def HasVSX : Predicate<"Subtarget->hasVSX()">;
397+
def NoP8Vector : Predicate<"!Subtarget->hasP8Vector()">;
398+
def HasP8Vector : Predicate<"Subtarget->hasP8Vector()">;
399+
def HasAltivec : Predicate<"Subtarget->hasAltivec()">;
400+
def HasP8Altivec : Predicate<"Subtarget->hasP8Altivec()">;
401+
def NoP9Vector : Predicate<"!Subtarget->hasP9Vector()">;
402+
def HasP9Vector : Predicate<"Subtarget->hasP9Vector()">;
403+
def NoP9Altivec : Predicate<"!Subtarget->hasP9Altivec()">;
404+
def HasP9Altivec : Predicate<"Subtarget->hasP9Altivec()">;
405+
def HasOnlySwappingMemOps : Predicate<"!Subtarget->hasP9Vector()">;
406+
def NoP10Vector: Predicate<"!Subtarget->hasP10Vector()">;
407+
def HasP10Vector: Predicate<"Subtarget->hasP10Vector()">;
408+
409+
// Predicates used to differenciate between different ISAs.
382410
def IsISA2_06 : Predicate<"Subtarget->isISA2_06()">;
383411
def IsISA2_07 : Predicate<"Subtarget->isISA2_07()">;
384412
def IsISA3_0 : Predicate<"Subtarget->isISA3_0()">;
385-
def HasFPU : Predicate<"Subtarget->hasFPU()">;
386-
def PCRelativeMemops : Predicate<"Subtarget->hasPCRelativeMemops()">;
413+
def IsISA3_1 : Predicate<"Subtarget->isISA3_1()">;
387414
def IsNotISA3_1 : Predicate<"!Subtarget->isISA3_1()">;
415+
def IsISAFuture : Predicate<"Subtarget->isISAFuture()">;
416+
def IsNotISAFuture : Predicate<"!Subtarget->isISAFuture()">;
388417

389418
// AIX assembler may not be modern enough to support some extended mne.
390419
def ModernAs: Predicate<"!Subtarget->isAIXABI() || Subtarget->HasModernAIXAs">,
391420
AssemblerPredicate<(any_of (not AIXOS), FeatureModernAIXAs)>;
392421
def IsAIX : Predicate<"Subtarget->isAIXABI()">;
393422
def NotAIX : Predicate<"!Subtarget->isAIXABI()">;
394-
def IsISAFuture : Predicate<"Subtarget->isISAFuture()">;
395-
def IsNotISAFuture : Predicate<"!Subtarget->isISAFuture()">;
396423

397424
//===----------------------------------------------------------------------===//
398425
// HwModes

‎llvm/lib/Target/PowerPC/PPCInstrAltivec.td‎

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -343,7 +343,6 @@ class VXCR_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty>
343343
//===----------------------------------------------------------------------===//
344344
// Instruction Definitions.
345345

346-
def HasAltivec : Predicate<"Subtarget->hasAltivec()">;
347346
let Predicates = [HasAltivec] in {
348347

349348
def DSS : DSS_Form<0, 822, (outs), (ins u5imm:$STRM),
@@ -1193,8 +1192,6 @@ class VX_VT5_VA5_VB5_XO9_o<bits<9> xo, string opc, list<dag> pattern>
11931192
let PS = 0;
11941193
}
11951194

1196-
def HasP8Altivec : Predicate<"Subtarget->hasP8Altivec()">;
1197-
def HasP8Crypto : Predicate<"Subtarget->hasP8Crypto()">;
11981195
let Predicates = [HasP8Altivec] in {
11991196

12001197
let isCommutable = 1 in {
@@ -1420,7 +1417,6 @@ def VSBOX : VXBX_Int_Ty<1480, "vsbox", int_ppc_altivec_crypto_vsbox, v2i64>;
14201417
} // HasP8Crypto
14211418

14221419
// The following altivec instructions were introduced in Power ISA 3.0
1423-
def HasP9Altivec : Predicate<"Subtarget->hasP9Altivec()">;
14241420
let Predicates = [HasP9Altivec] in {
14251421

14261422
// Vector Multiply-Sum

‎llvm/lib/Target/PowerPC/PPCInstrHTM.td‎

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -11,10 +11,6 @@
1111
//
1212
//===----------------------------------------------------------------------===//
1313

14-
15-
16-
def HasHTM : Predicate<"Subtarget->hasHTM()">;
17-
1814
def HTM_get_imm : SDNodeXForm<imm, [{
1915
return getI32Imm (N->getZExtValue(), SDLoc(N));
2016
}]>;

‎llvm/lib/Target/PowerPC/PPCInstrInfo.td‎

Lines changed: 9 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1282,7 +1282,7 @@ def RESTORE_CRBIT : PPCEmitTimePseudo<(outs crbitrc:$cond), (ins memri:$F),
12821282
let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, hasSideEffects = 0 in {
12831283
let isPredicable = 1, isReturn = 1, Uses = [LR, RM] in
12841284
def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,
1285-
[(PPCretglue)]>, Requires<[In32BitMode]>;
1285+
[(PPCretglue)]>, Requires<[IsPPC32]>;
12861286
let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in {
12871287
let isPredicable = 1 in
12881288
def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
@@ -1455,7 +1455,7 @@ let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
14551455
let isPredicable = 1 in
14561456
def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
14571457
"bctrl", IIC_BrB, [(PPCbctrl)]>,
1458-
Requires<[In32BitMode]>;
1458+
Requires<[IsPPC32]>;
14591459

14601460
let isCodeGenOnly = 1 in {
14611461
def BCCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins (pred $BIBO, $CR):$cond),
@@ -1541,7 +1541,7 @@ let isCall = 1, PPC970_Unit = 7, Defs = [LR, RM], isCodeGenOnly = 1 in {
15411541
let isPredicable = 1 in
15421542
def BCTRL_RM : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
15431543
"bctrl", IIC_BrB, [(PPCbctrl_rm)]>,
1544-
Requires<[In32BitMode]>;
1544+
Requires<[IsPPC32]>;
15451545
}
15461546
}
15471547

@@ -1567,7 +1567,7 @@ let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1,
15671567
def BCTRL_LWZinto_toc:
15681568
XLForm_2_ext_and_DForm_1<19, 528, 20, 0, 1, 32, (outs),
15691569
(ins (memri $D, $RA):$addr), "bctrl\n\tlwz 2, $addr", IIC_BrB,
1570-
[(PPCbctrl_load_toc iaddr:$addr)]>, Requires<[In32BitMode]>;
1570+
[(PPCbctrl_load_toc iaddr:$addr)]>, Requires<[IsPPC32]>;
15711571

15721572
}
15731573

@@ -1576,7 +1576,7 @@ let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1,
15761576
def BCTRL_LWZinto_toc_RM:
15771577
XLForm_2_ext_and_DForm_1<19, 528, 20, 0, 1, 32, (outs),
15781578
(ins (memri $D, $RA):$addr), "bctrl\n\tlwz 2, $addr", IIC_BrB,
1579-
[(PPCbctrl_load_toc_rm iaddr:$addr)]>, Requires<[In32BitMode]>;
1579+
[(PPCbctrl_load_toc_rm iaddr:$addr)]>, Requires<[IsPPC32]>;
15801580

15811581
}
15821582

@@ -1585,7 +1585,7 @@ let isCodeGenOnly = 1, hasSideEffects = 0 in {
15851585
let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
15861586
isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
15871587
def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
1588-
[]>, Requires<[In32BitMode]>;
1588+
[]>, Requires<[IsPPC32]>;
15891589

15901590
let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
15911591
isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
@@ -1608,15 +1608,15 @@ let hasSideEffects = 1 in {
16081608
def EH_SjLj_SetJmp32 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins memr:$buf),
16091609
"#EH_SJLJ_SETJMP32",
16101610
[(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
1611-
Requires<[In32BitMode]>;
1611+
Requires<[IsPPC32]>;
16121612
}
16131613

16141614
let hasSideEffects = 1, isBarrier = 1 in {
16151615
let isTerminator = 1 in
16161616
def EH_SjLj_LongJmp32 : PPCCustomInserterPseudo<(outs), (ins memr:$buf),
16171617
"#EH_SJLJ_LONGJMP32",
16181618
[(PPCeh_sjlj_longjmp addr:$buf)]>,
1619-
Requires<[In32BitMode]>;
1619+
Requires<[IsPPC32]>;
16201620
}
16211621

16221622
// This pseudo is never removed from the function, as it serves as
@@ -3438,8 +3438,6 @@ def Msk2Imm : ImmLeaf<i32, [{ return isUInt<2>(Imm); }]>;
34383438
def Msk4Imm : ImmLeaf<i32, [{ return isUInt<4>(Imm); }]>;
34393439
def Msk8Imm : ImmLeaf<i32, [{ return isUInt<8>(Imm); }]>;
34403440

3441-
def MMA : Predicate<"Subtarget->hasMMA()">;
3442-
34433441
// Prefixed instructions may require access to the above defs at a later
34443442
// time so we include this after the def.
34453443
include "PPCInstrP10.td"
@@ -5146,7 +5144,7 @@ def RotateInsertByte1 {
51465144
// Clear the upper half of the register when in 64-bit mode
51475145
let Predicates = [In64BitMode] in
51485146
def : Pat<(i32 (bitreverse i32:$A)), (RLDICL_32 RotateInsertByte1.Left, 0, 32)>;
5149-
let Predicates = [In32BitMode] in
5147+
let Predicates = [IsPPC32] in
51505148
def : Pat<(i32 (bitreverse i32:$A)), RotateInsertByte1.Left>;
51515149

51525150
// Fast 64-bit reverse bits algorithm:

‎llvm/lib/Target/PowerPC/PPCInstrP10.td‎

Lines changed: 0 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -51,10 +51,6 @@
5151
// Moreover, the order of operands reflects the order of operands
5252
// in the encoding.
5353

54-
//-------------------------- Predicate definitions ---------------------------//
55-
def IsPPC32 : Predicate<"!Subtarget->isPPC64()">;
56-
57-
5854
//===----------------------------------------------------------------------===//
5955
// PowerPC ISA 3.1 specific type constraints.
6056
//
@@ -634,9 +630,6 @@ multiclass 8LS_DForm_R_SI34_XT6_RA5_MEM_p<bits<5> opcode, dag OOL, dag IOL,
634630
}
635631
}
636632

637-
def PrefixInstrs : Predicate<"Subtarget->hasPrefixInstrs()">;
638-
def IsISA3_1 : Predicate<"Subtarget->isISA3_1()">;
639-
def PairedVectorMemops : Predicate<"Subtarget->pairedVectorMemops()">;
640633
def RCCp {
641634
dag AToVSRC = (COPY_TO_REGCLASS $XA, VSRC);
642635
dag BToVSRC = (COPY_TO_REGCLASS $XB, VSRC);

‎llvm/lib/Target/PowerPC/PPCInstrVSX.td‎

Lines changed: 0 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -116,20 +116,6 @@ def PPCSToV : SDNode<"PPCISD::SCALAR_TO_VECTOR_PERMUTED",
116116
SDTypeProfile<1, 1, []>, []>;
117117

118118
def PPCxxperm : SDNode<"PPCISD::XXPERM", SDT_PPCxxperm, []>;
119-
//-------------------------- Predicate definitions ---------------------------//
120-
def HasVSX : Predicate<"Subtarget->hasVSX()">;
121-
def IsLittleEndian : Predicate<"Subtarget->isLittleEndian()">;
122-
def IsBigEndian : Predicate<"!Subtarget->isLittleEndian()">;
123-
def IsPPC64 : Predicate<"Subtarget->isPPC64()">;
124-
def HasOnlySwappingMemOps : Predicate<"!Subtarget->hasP9Vector()">;
125-
def NoP8Vector : Predicate<"!Subtarget->hasP8Vector()">;
126-
def HasP8Vector : Predicate<"Subtarget->hasP8Vector()">;
127-
def HasDirectMove : Predicate<"Subtarget->hasDirectMove()">;
128-
def NoP9Vector : Predicate<"!Subtarget->hasP9Vector()">;
129-
def HasP9Vector : Predicate<"Subtarget->hasP9Vector()">;
130-
def NoP9Altivec : Predicate<"!Subtarget->hasP9Altivec()">;
131-
def NoP10Vector: Predicate<"!Subtarget->hasP10Vector()">;
132-
def HasP10Vector: Predicate<"Subtarget->hasP10Vector()">;
133119

134120
def PPCldsplatAlign16 : PatFrag<(ops node:$ptr), (PPCldsplat node:$ptr), [{
135121
return cast<MemIntrinsicSDNode>(N)->getAlign() >= Align(16) &&

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