We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
There was an error while loading. Please reload this page.
1 parent 9571cc2 commit fcacda8Copy full SHA for fcacda8
llvm/lib/Target/RISCV/RISCVCombine.td
@@ -24,6 +24,6 @@ def RISCVO0PreLegalizerCombiner: GICombiner<
24
def RISCVPostLegalizerCombiner
25
: GICombiner<"RISCVPostLegalizerCombinerImpl",
26
[sub_to_add, combines_for_extload, redundant_and,
27
- identity_combines, shift_immed_chain, commute_constant_to_rhs,
28
- constant_fold_cast_op]> {
+ identity_combines, shift_immed_chain,
+ commute_constant_to_rhs]> {
29
}
0 commit comments