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Aleksei Romanov
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[RISCV][AsmParser] Support parsing vset{i}vli omitting LMUL
This enables support of vset{i}vli instructions omitting LMUL corresponding to RISC-V specification.
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-39
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3 files changed

+52
-39
lines changed

‎llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp‎

Lines changed: 9 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2222,8 +2222,14 @@ bool RISCVAsmParser::parseVTypeToken(const AsmToken &Tok, VTypeState &State,
22222222
State = VTypeState_LMUL;
22232223
return false;
22242224
case VTypeState_LMUL: {
2225-
if (!Identifier.consume_front("m"))
2226-
break;
2225+
// Set LMUL to default if it is omitted.
2226+
if (!Identifier.consume_front("m")) {
2227+
Lmul = 1;
2228+
Fractional = false;
2229+
State = VTypeState_TailPolicy;
2230+
return parseVTypeToken(Tok, State, Sew, Lmul, Fractional, TailAgnostic,
2231+
MaskAgnostic);
2232+
}
22272233
Fractional = Identifier.consume_front("f");
22282234
if (Identifier.getAsInteger(10, Lmul))
22292235
break;
@@ -2320,7 +2326,7 @@ bool RISCVAsmParser::generateVTypeError(SMLoc ErrorLoc) {
23202326
return Error(
23212327
ErrorLoc,
23222328
"operand must be "
2323-
"e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]");
2329+
"e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}");
23242330
}
23252331

23262332
ParseStatus RISCVAsmParser::parseMaskReg(OperandVector &Operands) {

‎llvm/test/MC/RISCV/rvv/invalid.s‎

Lines changed: 30 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -1,102 +1,96 @@
11
# RUN: not llvm-mc -triple=riscv64 --mattr=+v --mattr=+f %s 2>&1 \
22
# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
33

4-
vsetvli a2, a0, e8, ta, ma
5-
# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
6-
7-
vsetivli a2, 16, e8, ta, ma
8-
# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
9-
104
vsetivli a2, 32, e8,m1
11-
# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
5+
# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
126

137
vsetivli a2, zero, e8,m1
14-
# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
8+
# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
159

1610
vsetivli a2, 5, (1 << 10)
17-
# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
11+
# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
1812

1913
vsetivli a2, 5, 0x400
20-
# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
14+
# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
2115

2216
vsetivli a2, 5, e31
23-
# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
17+
# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
2418

2519
vsetvli a2, a0, (1 << 11)
26-
# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
20+
# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
2721

2822
vsetvli a2, a0, 0x800
29-
# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
23+
# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
3024

3125

3226
vsetvli a2, a0, e31
33-
# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
27+
# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
3428

3529
vsetvli a2, a0, e32,m3
36-
# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
30+
# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
3731

3832
vsetvli a2, a0, m1,e32
39-
# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
33+
# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
4034

4135
vsetvli a2, a0, e32,m16
42-
# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
36+
# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
4337

4438
vsetvli a2, a0, e128,m8
45-
# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
39+
# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
4640

4741
vsetvli a2, a0, e256,m8
48-
# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
42+
# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
4943

5044
vsetvli a2, a0, e512,m8
51-
# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
45+
# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
5246

5347
vsetvli a2, a0, e1024,m8
54-
# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
48+
# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
5549

5650
vsetvli a2, a0, e2048,m8
57-
# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
51+
# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
5852

5953
vsetvli a2, a0, e1,m8
60-
# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
54+
# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
6155

6256
vsetvli a2, a0, e8,m1,tx
63-
# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
57+
# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
6458

6559
vsetvli a2, a0, e8,m1,ta,mx
66-
# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
60+
# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
6761

6862
vsetvli a2, a0, e8,m1,ma
69-
# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
63+
# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
7064

7165
vsetvli a2, a0, e8,m1,mu
72-
# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
66+
# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
7367

7468
vsetvli a2, a0, e8x,m1,tu,mu
75-
# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
69+
# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
7670

7771
vsetvli a2, a0, e8,m1z,tu,mu
78-
# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
72+
# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
7973

8074
vsetvli a2, a0, e8,mf1,tu,mu
81-
# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
75+
# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
8276

8377
vsetvli a2, a0, e8,m1,tu,mut
84-
# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
78+
# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
8579

8680
vsetvli a2, a0, e8,m1,tut,mu
87-
# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
81+
# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
8882

8983
vsetvli a2, a0, e8
90-
# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
84+
# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
9185

9286
vsetvli a2, a0, e8,m1
93-
# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
87+
# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
9488

9589
vsetvli a2, a0, e8,m1,ta
96-
# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
90+
# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
9791

9892
vsetvli a2, a0, e8,1,ta,ma
99-
# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
93+
# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
10094

10195
vadd.vv v1, v3, v2, v4.t
10296
# CHECK-ERROR: operand must be v0.t

‎llvm/test/MC/RISCV/rvv/vsetvl.s‎

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,19 @@
1010
# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+v %s \
1111
# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
1212

13+
# LMUL is omitted.
14+
vsetvli a2, a0, e8, ta, ma
15+
# CHECK-INST: vsetvli a2, a0, e8, m1, ta, ma
16+
# CHECK-ENCODING: [0x57,0x76,0x05,0x0c]
17+
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
18+
# CHECK-UNKNOWN: 0c057657 <unknown>
19+
20+
vsetivli a2, 16, e8, ta, ma
21+
# CHECK-INST: vsetivli a2, 16, e8, m1, ta, ma
22+
# CHECK-ENCODING: [0x57,0x76,0x08,0xcc]
23+
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
24+
# CHECK-UNKNOWN: cc087657 <unknown>
25+
1326
# reserved filed: vlmul[2:0]=4, vsew[2:0]=0b1xx, non-zero bits 8/9/10.
1427
vsetvli a2, a0, 0x224
1528
# CHECK-INST: vsetvli a2, a0, 548

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