Address comments

Author: V-FEXrt

clang/lib/CodeGen/CGBuiltin.cpp

@@ -19109,20 +19109,19 @@ case Builtin::BI__builtin_hlsl_elementwise_isinf: {
         ArrayRef<Value *>{Op0, Op1}, nullptr, "hlsl.step");
   }
   case Builtin::BI__builtin_hlsl_wave_active_any_true: {
-    IntegerType *Int1Ty =
-        llvm::Type::getInt1Ty(CGM.getTypes().getLLVMContext());
     Value *Op = EmitScalarExpr(E->getArg(0));
-    assert(Op->getType() == Int1Ty &&
-           "wave_active_any_true operand must be a bool");
+    llvm::Type *Ty = Op->getType();
+    assert(Ty->isIntegerTy(1) && "wave_active_any_true operand must be a bool");
 
     llvm::FunctionType *FT =
-        llvm::FunctionType::get(Int1Ty, {Int1Ty}, /*isVarArg=*/false);
+        llvm::FunctionType::get(Ty, {Ty}, /*isVarArg=*/false);
     llvm::StringRef Name = Intrinsic::getName(
         CGM.getHLSLRuntime().getWaveActiveAnyTrueIntrinsic());
     return EmitRuntimeCall(CGM.CreateRuntimeFunction(FT, Name, {},
                                                      /*Local=*/false,
                                                      /*AssumeConvergent=*/true),
                            {Op}, "hlsl.wave.activeanytrue");
+  }
   case Builtin::BI__builtin_hlsl_wave_active_count_bits: {
     Value *OpExpr = EmitScalarExpr(E->getArg(0));
     Intrinsic::ID ID = CGM.getHLSLRuntime().getWaveActiveCountBitsIntrinsic();

clang/lib/Sema/SemaHLSL.cpp

@@ -2091,12 +2091,6 @@ bool SemaHLSL::CheckBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) {
       return true;
     break;
   }
-  case Builtin::BI__builtin_hlsl_wave_active_any_true: {
-    if (SemaRef.checkArgCount(TheCall, 1))
-      return true;
-
-    break;
-  }
   case Builtin::BI__builtin_hlsl_wave_read_lane_at: {
     if (SemaRef.checkArgCount(TheCall, 2))
       return true;

clang/test/CodeGenHLSL/builtins/WaveActiveAnyTrue.hlsl

@@ -1,7 +1,7 @@
-// RUN: %clang_cc1 -std=hlsl2021 -finclude-default-header -fnative-half-type -triple \
+// RUN: %clang_cc1 -finclude-default-header -fnative-half-type -triple \
 // RUN:   dxil-pc-shadermodel6.3-compute %s -emit-llvm -disable-llvm-passes -o - | \
 // RUN:   FileCheck %s --check-prefixes=CHECK,CHECK-DXIL
-// RUN: %clang_cc1 -std=hlsl2021 -finclude-default-header -fnative-half-type -triple \
+// RUN: %clang_cc1 -finclude-default-header -fnative-half-type -triple \
 // RUN:   spirv-pc-vulkan-compute %s -emit-llvm -disable-llvm-passes -o - | \
 // RUN:   FileCheck %s --check-prefixes=CHECK,CHECK-SPIRV
 

llvm/lib/Target/DirectX/DXIL.td

@@ -202,7 +202,6 @@ defset list<DXILOpClass> OpClasses = {
   def unpack4x8 : DXILOpClass;
   def viewID : DXILOpClass;
   def waveActiveAllEqual : DXILOpClass;
-  def waveActiveAnyTrue : DXILOpClass;
   def waveActiveBallot : DXILOpClass;
   def waveActiveBit : DXILOpClass;
   def waveActiveOp : DXILOpClass;
@@ -854,7 +853,7 @@ def CreateHandleFromBinding : DXILOp<217, createHandleFromBinding> {
   let stages = [Stages<DXIL1_6, [all_stages]>];
 }
 
-def WaveActiveAnyTrue : DXILOp<113, waveActiveAnyTrue> {
+def WaveActiveAnyTrue : DXILOp<113, waveAnyTrue> {
   let Doc = "returns true if the expression is true in any of the active lanes in the current wave";
   let LLVMIntrinsic = int_dx_wave_activeanytrue;
   let arguments = [Int1Ty];

llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp

@@ -1929,15 +1929,13 @@ bool SPIRVInstructionSelector::selectWaveActiveAnyTrue(Register ResVReg,
   assert(I.getNumOperands() == 3);
   assert(I.getOperand(2).isReg());
 
-  // IntTy is used to define the execution scope, set to 3 to denote a
-  // cross-lane interaction equivalent to a SPIR-V subgroup.
   MachineBasicBlock &BB = *I.getParent();
   SPIRVType *IntTy = GR.getOrCreateSPIRVIntegerType(32, I, TII);
 
   return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpGroupNonUniformAny))
       .addDef(ResVReg)
       .addUse(GR.getSPIRVTypeID(ResType))
-      .addUse(GR.getOrCreateConstInt(3, I, IntTy, TII))
+      .addUse(GR.getOrCreateConstInt(SPIRV::Scope::Subgroup, I, IntTy, TII))
       .addUse(I.getOperand(2).getReg());
 }
 
@@ -1987,7 +1985,7 @@ bool SPIRVInstructionSelector::selectWaveReadLaneAt(Register ResVReg,
                  TII.get(SPIRV::OpGroupNonUniformShuffle))
       .addDef(ResVReg)
       .addUse(GR.getSPIRVTypeID(ResType))
-      .addUse(GR.getOrCreateConstInt(3, I, IntTy, TII))
+      .addUse(GR.getOrCreateConstInt(SPIRV::Scope::Subgroup, I, IntTy, TII))
       .addUse(I.getOperand(2).getReg())
       .addUse(I.getOperand(3).getReg());
 }

llvm/test/CodeGen/DirectX/WaveActiveAnyTrue.ll

@@ -2,7 +2,7 @@
 
 define noundef i1 @wave_aat_simple(i1 noundef %p1) {
 entry:
-; CHECK: call i1 @dx.op.waveActiveAnyTrue(i32 113, i1 %p1)
+; CHECK: call i1 @dx.op.waveAnyTrue(i32 113, i1 %p1)
   %ret = call i1 @llvm.dx.wave.activeanytrue(i1 %p1)
   ret i1 %ret
 }

llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveActiveAnyTrue.ll

@@ -1,5 +1,5 @@
-; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32v1.3-vulkan-unknown %s -o - | FileCheck %s
-; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32v1.3-vulkan-unknown %s -o - -filetype=obj | spirv-val %}
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32v1.5-unknown-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32v1.5-unknown-unknown %s -o - -filetype=obj | spirv-val %}
 
 ; CHECK: %[[#bool:]] = OpTypeBool
 ; CHECK: %[[#uint:]] = OpTypeInt 32 0