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[AggressiveAntiDepBreaker] Use MCRegister. NFC
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2 files changed

+79
-73
lines changed

2 files changed

+79
-73
lines changed

‎llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp‎

Lines changed: 62 additions & 57 deletions
Original file line numberDiff line numberDiff line change
@@ -67,7 +67,7 @@ AggressiveAntiDepState::AggressiveAntiDepState(const unsigned TargetRegs,
6767
}
6868
}
6969

70-
unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) {
70+
unsigned AggressiveAntiDepState::GetGroup(MCRegister Reg) {
7171
unsigned Node = GroupNodeIndices[Reg];
7272
while (GroupNodes[Node] != Node)
7373
Node = GroupNodes[Node];
@@ -76,17 +76,16 @@ unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) {
7676
}
7777

7878
void AggressiveAntiDepState::GetGroupRegs(
79-
unsigned Group,
80-
std::vector<unsigned> &Regs,
81-
std::multimap<unsigned, AggressiveAntiDepState::RegisterReference> *RegRefs)
82-
{
79+
unsigned Group, std::vector<MCRegister> &Regs,
80+
std::multimap<MCRegister, AggressiveAntiDepState::RegisterReference>
81+
*RegRefs) {
8382
for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) {
8483
if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0))
8584
Regs.push_back(Reg);
8685
}
8786
}
8887

89-
unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2) {
88+
unsigned AggressiveAntiDepState::UnionGroups(MCRegister Reg1, MCRegister Reg2) {
9089
assert(GroupNodes[0] == 0 && "GroupNode 0 not parent!");
9190
assert(GroupNodeIndices[0] == 0 && "Reg 0 not in Group 0!");
9291

@@ -101,7 +100,7 @@ unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2) {
101100
return Parent;
102101
}
103102

104-
unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg) {
103+
unsigned AggressiveAntiDepState::LeaveGroup(MCRegister Reg) {
105104
// Create a new GroupNode for Reg. Reg's existing GroupNode must
106105
// stay as is because there could be other GroupNodes referring to
107106
// it.
@@ -111,7 +110,7 @@ unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg) {
111110
return idx;
112111
}
113112

114-
bool AggressiveAntiDepState::IsLive(unsigned Reg) {
113+
bool AggressiveAntiDepState::IsLive(MCRegister Reg) {
115114
// KillIndex must be defined and DefIndex not defined for a register
116115
// to be live.
117116
return((KillIndices[Reg] != ~0u) && (DefIndices[Reg] == ~0u));
@@ -173,7 +172,7 @@ void AggressiveAntiDepBreaker::StartBlock(MachineBasicBlock *BB) {
173172
if (!IsReturnBlock && !Pristine.test(Reg))
174173
continue;
175174
for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
176-
unsigned AliasReg = *AI;
175+
MCRegister AliasReg = *AI;
177176
State->UnionGroups(AliasReg, 0);
178177
KillIndices[AliasReg] = BB->size();
179178
DefIndices[AliasReg] = ~0u;
@@ -190,7 +189,7 @@ void AggressiveAntiDepBreaker::Observe(MachineInstr &MI, unsigned Count,
190189
unsigned InsertPosIndex) {
191190
assert(Count < InsertPosIndex && "Instruction index out of expected range!");
192191

193-
std::set<unsigned> PassthruRegs;
192+
std::set<MCRegister> PassthruRegs;
194193
GetPassthruRegs(MI, PassthruRegs);
195194
PrescanInstruction(MI, Count, PassthruRegs);
196195
ScanInstruction(MI, Count);
@@ -239,7 +238,7 @@ bool AggressiveAntiDepBreaker::IsImplicitDefUse(MachineInstr &MI,
239238
}
240239

241240
void AggressiveAntiDepBreaker::GetPassthruRegs(
242-
MachineInstr &MI, std::set<unsigned> &PassthruRegs) {
241+
MachineInstr &MI, std::set<MCRegister> &PassthruRegs) {
243242
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
244243
MachineOperand &MO = MI.getOperand(i);
245244
if (!MO.isReg()) continue;
@@ -288,14 +287,14 @@ static const SUnit *CriticalPathStep(const SUnit *SU) {
288287
return (Next) ? Next->getSUnit() : nullptr;
289288
}
290289

291-
void AggressiveAntiDepBreaker::HandleLastUse(unsigned Reg, unsigned KillIdx,
290+
void AggressiveAntiDepBreaker::HandleLastUse(MCRegister Reg, unsigned KillIdx,
292291
const char *tag,
293292
const char *header,
294293
const char *footer) {
295294
std::vector<unsigned> &KillIndices = State->GetKillIndices();
296295
std::vector<unsigned> &DefIndices = State->GetDefIndices();
297-
std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
298-
RegRefs = State->GetRegRefs();
296+
std::multimap<MCRegister, AggressiveAntiDepState::RegisterReference>
297+
&RegRefs = State->GetRegRefs();
299298

300299
// FIXME: We must leave subregisters of live super registers as live, so that
301300
// we don't clear out the register tracking information for subregisters of
@@ -341,10 +340,11 @@ void AggressiveAntiDepBreaker::HandleLastUse(unsigned Reg, unsigned KillIdx,
341340
}
342341

343342
void AggressiveAntiDepBreaker::PrescanInstruction(
344-
MachineInstr &MI, unsigned Count, std::set<unsigned> &PassthruRegs) {
343+
MachineInstr &MI, unsigned Count,
344+
const std::set<MCRegister> &PassthruRegs) {
345345
std::vector<unsigned> &DefIndices = State->GetDefIndices();
346-
std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
347-
RegRefs = State->GetRegRefs();
346+
std::multimap<MCRegister, AggressiveAntiDepState::RegisterReference>
347+
&RegRefs = State->GetRegRefs();
348348

349349
// Handle dead defs by simulating a last-use of the register just
350350
// after the def. A dead def can occur because the def is truly
@@ -353,17 +353,19 @@ void AggressiveAntiDepBreaker::PrescanInstruction(
353353
// previous def.
354354
for (const MachineOperand &MO : MI.all_defs()) {
355355
Register Reg = MO.getReg();
356-
if (Reg == 0) continue;
356+
if (!Reg)
357+
continue;
357358

358-
HandleLastUse(Reg, Count + 1, "", "\tDead Def: ", "\n");
359+
HandleLastUse(Reg.asMCReg(), Count + 1, "", "\tDead Def: ", "\n");
359360
}
360361

361362
LLVM_DEBUG(dbgs() << "\tDef Groups:");
362363
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
363364
MachineOperand &MO = MI.getOperand(i);
364365
if (!MO.isReg() || !MO.isDef()) continue;
365366
Register Reg = MO.getReg();
366-
if (Reg == 0) continue;
367+
if (!Reg)
368+
continue;
367369

368370
LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI) << "=g"
369371
<< State->GetGroup(Reg));
@@ -382,7 +384,7 @@ void AggressiveAntiDepBreaker::PrescanInstruction(
382384
// Any aliased that are live at this point are completely or
383385
// partially defined here, so group those aliases with Reg.
384386
for (MCRegAliasIterator AI(Reg, TRI, false); AI.isValid(); ++AI) {
385-
unsigned AliasReg = *AI;
387+
MCRegister AliasReg = *AI;
386388
if (State->IsLive(AliasReg)) {
387389
State->UnionGroups(Reg, AliasReg);
388390
LLVM_DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << "(via "
@@ -404,7 +406,8 @@ void AggressiveAntiDepBreaker::PrescanInstruction(
404406
// live-ranges.
405407
for (const MachineOperand &MO : MI.all_defs()) {
406408
Register Reg = MO.getReg();
407-
if (Reg == 0) continue;
409+
if (!Reg)
410+
continue;
408411
// Ignore KILLs and passthru registers for liveness...
409412
if (MI.isKill() || (PassthruRegs.count(Reg) != 0))
410413
continue;
@@ -428,8 +431,8 @@ void AggressiveAntiDepBreaker::PrescanInstruction(
428431
void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr &MI,
429432
unsigned Count) {
430433
LLVM_DEBUG(dbgs() << "\tUse Groups:");
431-
std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
432-
RegRefs = State->GetRegRefs();
434+
std::multimap<MCRegister, AggressiveAntiDepState::RegisterReference>
435+
&RegRefs = State->GetRegRefs();
433436

434437
// If MI's uses have special allocation requirement, don't allow
435438
// any use registers to be changed. Also assume all registers
@@ -457,15 +460,16 @@ void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr &MI,
457460
MachineOperand &MO = MI.getOperand(i);
458461
if (!MO.isReg() || !MO.isUse()) continue;
459462
Register Reg = MO.getReg();
460-
if (Reg == 0) continue;
463+
if (!Reg)
464+
continue;
461465

462466
LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI) << "=g"
463467
<< State->GetGroup(Reg));
464468

465469
// It wasn't previously live but now it is, this is a kill. Forget
466470
// the previous live-range information and start a new live-range
467471
// for the register.
468-
HandleLastUse(Reg, Count, "(last-use)");
472+
HandleLastUse(Reg.asMCReg(), Count, "(last-use)");
469473

470474
if (Special) {
471475
LLVM_DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)");
@@ -487,13 +491,14 @@ void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr &MI,
487491
if (MI.isKill()) {
488492
LLVM_DEBUG(dbgs() << "\tKill Group:");
489493

490-
unsigned FirstReg = 0;
494+
Register FirstReg;
491495
for (const MachineOperand &MO : MI.operands()) {
492496
if (!MO.isReg()) continue;
493497
Register Reg = MO.getReg();
494-
if (Reg == 0) continue;
498+
if (!Reg)
499+
continue;
495500

496-
if (FirstReg != 0) {
501+
if (FirstReg) {
497502
LLVM_DEBUG(dbgs() << "=" << printReg(Reg, TRI));
498503
State->UnionGroups(FirstReg, Reg);
499504
} else {
@@ -506,7 +511,7 @@ void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr &MI,
506511
}
507512
}
508513

509-
BitVector AggressiveAntiDepBreaker::GetRenameRegisters(unsigned Reg) {
514+
BitVector AggressiveAntiDepBreaker::GetRenameRegisters(MCRegister Reg) {
510515
BitVector BV(TRI->getNumRegs(), false);
511516
bool first = true;
512517

@@ -532,17 +537,17 @@ BitVector AggressiveAntiDepBreaker::GetRenameRegisters(unsigned Reg) {
532537
}
533538

534539
bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
535-
unsigned SuperReg, unsigned AntiDepGroupIndex, RenameOrderType &RenameOrder,
536-
std::map<unsigned, unsigned> &RenameMap) {
540+
MCRegister SuperReg, unsigned AntiDepGroupIndex,
541+
RenameOrderType &RenameOrder, std::map<MCRegister, MCRegister> &RenameMap) {
537542
std::vector<unsigned> &KillIndices = State->GetKillIndices();
538543
std::vector<unsigned> &DefIndices = State->GetDefIndices();
539-
std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
540-
RegRefs = State->GetRegRefs();
544+
std::multimap<MCRegister, AggressiveAntiDepState::RegisterReference>
545+
&RegRefs = State->GetRegRefs();
541546

542547
// Collect all referenced registers in the same group as
543548
// AntiDepReg. These all need to be renamed together if we are to
544549
// break the anti-dependence.
545-
std::vector<unsigned> Regs;
550+
std::vector<MCRegister> Regs;
546551
State->GetGroupRegs(AntiDepGroupIndex, Regs, &RegRefs);
547552
assert(!Regs.empty() && "Empty register group!");
548553
if (Regs.empty())
@@ -552,8 +557,8 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
552557
// each register.
553558
LLVM_DEBUG(dbgs() << "\tRename Candidates for Group g" << AntiDepGroupIndex
554559
<< ":\n");
555-
std::map<unsigned, BitVector> RenameRegisterMap;
556-
for (unsigned Reg : Regs) {
560+
std::map<MCRegister, BitVector> RenameRegisterMap;
561+
for (MCRegister Reg : Regs) {
557562
// If Reg has any references, then collect possible rename regs
558563
if (RegRefs.count(Reg) > 0) {
559564
LLVM_DEBUG(dbgs() << "\t\t" << printReg(Reg, TRI) << ":");
@@ -572,7 +577,7 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
572577
}
573578

574579
// All group registers should be a subreg of SuperReg.
575-
for (unsigned Reg : Regs) {
580+
for (MCRegister Reg : Regs) {
576581
if (Reg == SuperReg) continue;
577582
bool IsSub = TRI->isSubRegister(SuperReg, Reg);
578583
// FIXME: remove this once PR18663 has been properly fixed. For now,
@@ -621,7 +626,7 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
621626
do {
622627
if (R == 0) R = Order.size();
623628
--R;
624-
const unsigned NewSuperReg = Order[R];
629+
const MCRegister NewSuperReg = Order[R];
625630
// Don't consider non-allocatable registers
626631
if (!MRI.isAllocatable(NewSuperReg)) continue;
627632
// Don't replace a register with itself.
@@ -633,8 +638,8 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
633638
// For each referenced group register (which must be a SuperReg or
634639
// a subregister of SuperReg), find the corresponding subregister
635640
// of NewSuperReg and make sure it is free to be renamed.
636-
for (unsigned Reg : Regs) {
637-
unsigned NewReg = 0;
641+
for (MCRegister Reg : Regs) {
642+
MCRegister NewReg;
638643
if (Reg == SuperReg) {
639644
NewReg = NewSuperReg;
640645
} else {
@@ -661,7 +666,7 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
661666
} else {
662667
bool found = false;
663668
for (MCRegAliasIterator AI(NewReg, TRI, false); AI.isValid(); ++AI) {
664-
unsigned AliasReg = *AI;
669+
MCRegister AliasReg = *AI;
665670
if (State->IsLive(AliasReg) ||
666671
(KillIndices[Reg] > DefIndices[AliasReg])) {
667672
LLVM_DEBUG(dbgs()
@@ -703,7 +708,7 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
703708
}
704709

705710
// Record that 'Reg' can be renamed to 'NewReg'.
706-
RenameMap.insert(std::pair<unsigned, unsigned>(Reg, NewReg));
711+
RenameMap.insert(std::make_pair(Reg, NewReg));
707712
}
708713

709714
// If we fall-out here, then every register in the group can be
@@ -733,8 +738,8 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
733738
DbgValueVector &DbgValues) {
734739
std::vector<unsigned> &KillIndices = State->GetKillIndices();
735740
std::vector<unsigned> &DefIndices = State->GetDefIndices();
736-
std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
737-
RegRefs = State->GetRegRefs();
741+
std::multimap<MCRegister, AggressiveAntiDepState::RegisterReference>
742+
&RegRefs = State->GetRegRefs();
738743

739744
// The code below assumes that there is at least one instruction,
740745
// so just duck out immediately if the block is empty.
@@ -792,7 +797,7 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
792797
LLVM_DEBUG(dbgs() << "Anti: ");
793798
LLVM_DEBUG(MI.dump());
794799

795-
std::set<unsigned> PassthruRegs;
800+
std::set<MCRegister> PassthruRegs;
796801
GetPassthruRegs(MI, PassthruRegs);
797802

798803
// Process the defs in MI...
@@ -824,15 +829,15 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
824829
if ((Edge->getKind() != SDep::Anti) &&
825830
(Edge->getKind() != SDep::Output)) continue;
826831

827-
unsigned AntiDepReg = Edge->getReg();
832+
MCRegister AntiDepReg = MCRegister::from(Edge->getReg());
828833
LLVM_DEBUG(dbgs() << "\tAntidep reg: " << printReg(AntiDepReg, TRI));
829-
assert(AntiDepReg != 0 && "Anti-dependence on reg0?");
834+
assert(AntiDepReg && "Anti-dependence on reg0?");
830835

831836
if (!MRI.isAllocatable(AntiDepReg)) {
832837
// Don't break anti-dependencies on non-allocatable registers.
833838
LLVM_DEBUG(dbgs() << " (non-allocatable)\n");
834839
continue;
835-
} else if (ExcludeRegs && ExcludeRegs->test(AntiDepReg)) {
840+
} else if (ExcludeRegs && ExcludeRegs->test(AntiDepReg.id())) {
836841
// Don't break anti-dependencies for critical path registers
837842
// if not on the critical path
838843
LLVM_DEBUG(dbgs() << " (not critical-path)\n");
@@ -867,30 +872,30 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
867872
Pred.getReg() != AntiDepReg)
868873
: (Pred.getKind() == SDep::Data &&
869874
Pred.getReg() == AntiDepReg)) {
870-
AntiDepReg = 0;
875+
AntiDepReg = MCRegister();
871876
break;
872877
}
873878
}
874879
for (const SDep &Pred : PathSU->Preds) {
875880
if ((Pred.getSUnit() == NextSU) && (Pred.getKind() != SDep::Anti) &&
876881
(Pred.getKind() != SDep::Output)) {
877882
LLVM_DEBUG(dbgs() << " (real dependency)\n");
878-
AntiDepReg = 0;
883+
AntiDepReg = MCRegister();
879884
break;
880885
} else if ((Pred.getSUnit() != NextSU) &&
881886
(Pred.getKind() == SDep::Data) &&
882887
(Pred.getReg() == AntiDepReg)) {
883888
LLVM_DEBUG(dbgs() << " (other dependency)\n");
884-
AntiDepReg = 0;
889+
AntiDepReg = MCRegister();
885890
break;
886891
}
887892
}
888893

889-
if (AntiDepReg == 0)
894+
if (!AntiDepReg)
890895
continue;
891896
}
892897

893-
assert(AntiDepReg != 0);
898+
assert(AntiDepReg);
894899

895900
// Determine AntiDepReg's register group.
896901
const unsigned GroupIndex = State->GetGroup(AntiDepReg);
@@ -902,16 +907,16 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
902907
LLVM_DEBUG(dbgs() << '\n');
903908

904909
// Look for a suitable register to use to break the anti-dependence.
905-
std::map<unsigned, unsigned> RenameMap;
910+
std::map<MCRegister, MCRegister> RenameMap;
906911
if (FindSuitableFreeRegisters(AntiDepReg, GroupIndex, RenameOrder,
907912
RenameMap)) {
908913
LLVM_DEBUG(dbgs() << "\tBreaking anti-dependence edge on "
909914
<< printReg(AntiDepReg, TRI) << ":");
910915

911916
// Handle each group register...
912917
for (const auto &P : RenameMap) {
913-
unsigned CurrReg = P.first;
914-
unsigned NewReg = P.second;
918+
MCRegister CurrReg = P.first;
919+
MCRegister NewReg = P.second;
915920

916921
LLVM_DEBUG(dbgs() << " " << printReg(CurrReg, TRI) << "->"
917922
<< printReg(NewReg, TRI) << "("

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