Address CR comment, pt.2

Remove the `mayAlias` check, and only check if there are any instructions between the loads we want to optimize that could be a load fold barrier instead.

Author: jcohen-apple

llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

@@ -7419,21 +7419,6 @@ static bool getMiscPatterns(MachineInstr &Root,
   return false;
 }
 
-/// Check if a given MachineInstr `MIa` may alias with any of the instructions
-/// in `MemInstrs`.
-static bool mayAlias(const MachineInstr &MIa,
-                     SmallVectorImpl<const MachineInstr *> &MemInstrs,
-                     AliasAnalysis *AA) {
-  for (const MachineInstr *MIb : MemInstrs) {
-    if (MIa.mayAlias(AA, *MIb, /*UseTBAA*/ false)) {
-      MIb->dump();
-      return true;
-    }
-  }
-
-  return false;
-}
-
 /// Check if the given instruction forms a gather load pattern that can be
 /// optimized for better Memory-Level Parallelism (MLP). This function
 /// identifies chains of NEON lane load instructions that load data from
@@ -7477,7 +7462,7 @@ static bool getGatherLanePattern(MachineInstr &Root,
   auto *CurrInstr = MRI.getUniqueVRegDef(Root.getOperand(1).getReg());
   auto Range = llvm::seq<unsigned>(1, NumLanes - 1);
   SmallSet<unsigned, 16> RemainingLanes(Range.begin(), Range.end());
-  SmallVector<const MachineInstr *, 16> LoadInstrs = {};
+  SmallVector<const MachineInstr *, 16> LoadInstrs;
   while (!RemainingLanes.empty() && CurrInstr &&
          CurrInstr->getOpcode() == LoadLaneOpCode &&
          MRI.hasOneNonDBGUse(CurrInstr->getOperand(0).getReg()) &&
@@ -7527,8 +7512,7 @@ static bool getGatherLanePattern(MachineInstr &Root,
 
     // Check for potential aliasing with any of the load instructions to
     // optimize.
-    if ((CurrInstr.mayLoadOrStore() || CurrInstr.isCall()) &&
-        mayAlias(CurrInstr, LoadInstrs, nullptr))
+    if (CurrInstr.isLoadFoldBarrier())
       return false;
   }