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YixingZhang007YixingZhang007
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code clean up
1 parent 8578a56 commit fd4a78f

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5 files changed

+79
-61
lines changed

5 files changed

+79
-61
lines changed

‎llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp‎

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -50,17 +50,18 @@ void SPIRVInstPrinter::printOpConstantVarOps(const MCInst *MI,
5050
unsigned IsBitwidth16 = MI->getFlags() & SPIRV::INST_PRINTER_WIDTH16;
5151
const unsigned NumVarOps = MI->getNumOperands() - StartIndex;
5252

53-
// we support integer up to 1024 bits
54-
assert((NumVarOps <= 1024) &&
53+
// We support integer up to 1024 bits
54+
assert((NumVarOps <= 32) &&
5555
"Unsupported number of bits for literal variable");
5656

5757
O << ' ';
5858

5959
// Handle arbitrary number of 32-bit words for the literal value.
60-
if (MI->getOpcode() == SPIRV::OpConstantI){
60+
if (MI->getOpcode() == SPIRV::OpConstantI) {
6161
APInt Val(NumVarOps * 32, 0);
6262
for (unsigned i = 0; i < NumVarOps; ++i) {
63-
Val |= (APInt(NumVarOps * 32, MI->getOperand(StartIndex + i).getImm()) << (i * 32));
63+
Val |= (APInt(NumVarOps * 32, MI->getOperand(StartIndex + i).getImm())
64+
<< (i * 32));
6465
}
6566
O << Val;
6667
return;

‎llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -356,8 +356,7 @@ Register SPIRVGlobalRegistry::getOrCreateConstInt(APInt Val, MachineInstr &I,
356356
return createConstInt(CI, Val, I, SpvType, TII, ZeroAsNull);
357357
}
358358

359-
Register SPIRVGlobalRegistry::createConstInt(const Constant *CI,
360-
APInt Val,
359+
Register SPIRVGlobalRegistry::createConstInt(const Constant *CI, APInt Val,
361360
MachineInstr &I,
362361
SPIRVType *SpvType,
363362
const SPIRVInstrInfo &TII,
@@ -492,8 +491,9 @@ Register SPIRVGlobalRegistry::getOrCreateBaseRegister(
492491
}
493492
assert(Type->getOpcode() == SPIRV::OpTypeInt);
494493
SPIRVType *SpvBaseType = getOrCreateSPIRVIntegerType(BitWidth, I, TII);
495-
return getOrCreateConstInt(APInt(BitWidth, Val->getUniqueInteger().getZExtValue()), I,
496-
SpvBaseType, TII, ZeroAsNull);
494+
return getOrCreateConstInt(
495+
APInt(BitWidth, Val->getUniqueInteger().getZExtValue()), I, SpvBaseType,
496+
TII, ZeroAsNull);
497497
}
498498

499499
Register SPIRVGlobalRegistry::getOrCreateCompositeOrNull(

‎llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -515,8 +515,8 @@ class SPIRVGlobalRegistry : public SPIRVIRMapping {
515515
Register buildConstantInt(uint64_t Val, MachineIRBuilder &MIRBuilder,
516516
SPIRVType *SpvType, bool EmitIR,
517517
bool ZeroAsNull = true);
518-
Register getOrCreateConstInt(APInt Val, MachineInstr &I,
519-
SPIRVType *SpvType, const SPIRVInstrInfo &TII,
518+
Register getOrCreateConstInt(APInt Val, MachineInstr &I, SPIRVType *SpvType,
519+
const SPIRVInstrInfo &TII,
520520
bool ZeroAsNull = true);
521521
Register createConstInt(const Constant *CI, APInt Val, MachineInstr &I,
522522
SPIRVType *SpvType, const SPIRVInstrInfo &TII,

‎llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp‎

Lines changed: 67 additions & 50 deletions
Original file line numberDiff line numberDiff line change
@@ -2247,33 +2247,36 @@ bool SPIRVInstructionSelector::selectDot4AddPackedExpansion(
22472247
for (unsigned i = 0; i < 4; i++) {
22482248
// A[i]
22492249
Register AElt = MRI->createVirtualRegister(&SPIRV::IDRegClass);
2250-
Result &=
2251-
BuildMI(BB, I, I.getDebugLoc(), TII.get(ExtractOp))
2252-
.addDef(AElt)
2253-
.addUse(GR.getSPIRVTypeID(ResType))
2254-
.addUse(X)
2255-
.addUse(GR.getOrCreateConstInt(APInt(8, i * 8), I, EltType, TII, ZeroAsNull))
2256-
.addUse(GR.getOrCreateConstInt(APInt(8, 8), I, EltType, TII, ZeroAsNull))
2257-
.constrainAllUses(TII, TRI, RBI);
2250+
Result &= BuildMI(BB, I, I.getDebugLoc(), TII.get(ExtractOp))
2251+
.addDef(AElt)
2252+
.addUse(GR.getSPIRVTypeID(ResType))
2253+
.addUse(X)
2254+
.addUse(GR.getOrCreateConstInt(APInt(8, i * 8), I, EltType,
2255+
TII, ZeroAsNull))
2256+
.addUse(GR.getOrCreateConstInt(APInt(8, 8), I, EltType, TII,
2257+
ZeroAsNull))
2258+
.constrainAllUses(TII, TRI, RBI);
22582259

22592260
// B[i]
2260-
Register BElt = MRI->createVirtualRegister(&SPIRV::IDRegClass);
2261-
Result &=
2262-
BuildMI(BB, I, I.getDebugLoc(), TII.get(ExtractOp))
2263-
.addDef(BElt)
2264-
.addUse(GR.getSPIRVTypeID(ResType))
2265-
.addUse(Y)
2266-
.addUse(GR.getOrCreateConstInt(APInt(8, i * 8), I, EltType, TII, ZeroAsNull))
2267-
.addUse(GR.getOrCreateConstInt(APInt(8, 8), I, EltType, TII, ZeroAsNull))
2268-
.constrainAllUses(TII, TRI, RBI);
2261+
Result &= BuildMI(BB, I, I.getDebugLoc(), TII.get(ExtractOp))
2262+
.addDef(BElt)
2263+
.addUse(GR.getSPIRVTypeID(ResType))
2264+
.addUse(Y)
2265+
.addUse(GR.getOrCreateConstInt(APInt(8, i * 8), I, EltType,
2266+
TII, ZeroAsNull))
2267+
.addUse(GR.getOrCreateConstInt(APInt(8, 8), I, EltType, TII,
2268+
ZeroAsNull))
2269+
.constrainAllUses(TII, TRI, RBI);
22692270

22702271
// A[i] * B[i]
2271-
Register Mul = MRI->createVirtualRegister(&SPIRV::IDRegClass);
2272-
Result &= BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpIMulS))
2273-
.addDef(Mul)
2272+
Result &= BuildMI(BB, I, I.getDebugLoc(), TII.get(ExtractOp))
2273+
.addDef(MaskMul)
22742274
.addUse(GR.getSPIRVTypeID(ResType))
2275-
.addUse(AElt)
2276-
.addUse(BElt)
2275+
.addUse(Mul)
2276+
.addUse(GR.getOrCreateConstInt(APInt(8, 0), I, EltType, TII,
2277+
ZeroAsNull))
2278+
.addUse(GR.getOrCreateConstInt(APInt(8, 8), I, EltType, TII,
2279+
ZeroAsNull))
22772280
.constrainAllUses(TII, TRI, RBI);
22782281

22792282
// Discard 24 highest-bits so that stored i32 register is i8 equivalent
@@ -2378,11 +2381,12 @@ bool SPIRVInstructionSelector::selectWaveOpInst(Register ResVReg,
23782381
MachineBasicBlock &BB = *I.getParent();
23792382
SPIRVType *IntTy = GR.getOrCreateSPIRVIntegerType(32, I, TII);
23802383

2381-
auto BMI = BuildMI(BB, I, I.getDebugLoc(), TII.get(Opcode))
2382-
.addDef(ResVReg)
2383-
.addUse(GR.getSPIRVTypeID(ResType))
2384-
.addUse(GR.getOrCreateConstInt(APInt(32, SPIRV::Scope::Subgroup), I,
2385-
IntTy, TII, !STI.isShader()));
2384+
auto BMI =
2385+
BuildMI(BB, I, I.getDebugLoc(), TII.get(Opcode))
2386+
.addDef(ResVReg)
2387+
.addUse(GR.getSPIRVTypeID(ResType))
2388+
.addUse(GR.getOrCreateConstInt(APInt(32, SPIRV::Scope::Subgroup), I,
2389+
IntTy, TII, !STI.isShader()));
23862390

23872391
for (unsigned J = 2; J < I.getNumOperands(); J++) {
23882392
BMI.addUse(I.getOperand(J).getReg());
@@ -2401,15 +2405,16 @@ bool SPIRVInstructionSelector::selectWaveActiveCountBits(
24012405
SPIRV::OpGroupNonUniformBallot);
24022406

24032407
MachineBasicBlock &BB = *I.getParent();
2404-
Result &= BuildMI(BB, I, I.getDebugLoc(),
2405-
TII.get(SPIRV::OpGroupNonUniformBallotBitCount))
2406-
.addDef(ResVReg)
2407-
.addUse(GR.getSPIRVTypeID(ResType))
2408-
.addUse(GR.getOrCreateConstInt(APInt(32, SPIRV::Scope::Subgroup), I, IntTy,
2409-
TII, !STI.isShader()))
2410-
.addImm(SPIRV::GroupOperation::Reduce)
2411-
.addUse(BallotReg)
2412-
.constrainAllUses(TII, TRI, RBI);
2408+
Result &=
2409+
BuildMI(BB, I, I.getDebugLoc(),
2410+
TII.get(SPIRV::OpGroupNonUniformBallotBitCount))
2411+
.addDef(ResVReg)
2412+
.addUse(GR.getSPIRVTypeID(ResType))
2413+
.addUse(GR.getOrCreateConstInt(APInt(32, SPIRV::Scope::Subgroup), I,
2414+
IntTy, TII, !STI.isShader()))
2415+
.addImm(SPIRV::GroupOperation::Reduce)
2416+
.addUse(BallotReg)
2417+
.constrainAllUses(TII, TRI, RBI);
24132418

24142419
return Result;
24152420
}
@@ -2436,8 +2441,8 @@ bool SPIRVInstructionSelector::selectWaveReduceMax(Register ResVReg,
24362441
return BuildMI(BB, I, I.getDebugLoc(), TII.get(Opcode))
24372442
.addDef(ResVReg)
24382443
.addUse(GR.getSPIRVTypeID(ResType))
2439-
.addUse(GR.getOrCreateConstInt(APInt(32, SPIRV::Scope::Subgroup), I, IntTy, TII,
2440-
!STI.isShader()))
2444+
.addUse(GR.getOrCreateConstInt(APInt(32, SPIRV::Scope::Subgroup), I,
2445+
IntTy, TII, !STI.isShader()))
24412446
.addImm(SPIRV::GroupOperation::Reduce)
24422447
.addUse(I.getOperand(2).getReg())
24432448
.constrainAllUses(TII, TRI, RBI);
@@ -2463,8 +2468,8 @@ bool SPIRVInstructionSelector::selectWaveReduceSum(Register ResVReg,
24632468
return BuildMI(BB, I, I.getDebugLoc(), TII.get(Opcode))
24642469
.addDef(ResVReg)
24652470
.addUse(GR.getSPIRVTypeID(ResType))
2466-
.addUse(GR.getOrCreateConstInt(APInt(32, SPIRV::Scope::Subgroup), I, IntTy, TII,
2467-
!STI.isShader()))
2471+
.addUse(GR.getOrCreateConstInt(APInt(32, SPIRV::Scope::Subgroup), I,
2472+
IntTy, TII, !STI.isShader()))
24682473
.addImm(SPIRV::GroupOperation::Reduce)
24692474
.addUse(I.getOperand(2).getReg());
24702475
}
@@ -2689,7 +2694,8 @@ Register SPIRVInstructionSelector::buildZerosVal(const SPIRVType *ResType,
26892694
bool ZeroAsNull = !STI.isShader();
26902695
if (ResType->getOpcode() == SPIRV::OpTypeVector)
26912696
return GR.getOrCreateConstVector(0UL, I, ResType, TII, ZeroAsNull);
2692-
return GR.getOrCreateConstInt(APInt(GR.getScalarOrVectorBitWidth(ResType), 0), I, ResType, TII, ZeroAsNull);
2697+
return GR.getOrCreateConstInt(APInt(GR.getScalarOrVectorBitWidth(ResType), 0),
2698+
I, ResType, TII, ZeroAsNull);
26932699
}
26942700

26952701
Register SPIRVInstructionSelector::buildZerosValF(const SPIRVType *ResType,
@@ -2720,7 +2726,9 @@ Register SPIRVInstructionSelector::buildOnesVal(bool AllOnes,
27202726
AllOnes ? APInt::getAllOnes(BitWidth) : APInt::getOneBitSet(BitWidth, 0);
27212727
if (ResType->getOpcode() == SPIRV::OpTypeVector)
27222728
return GR.getOrCreateConstVector(One.getZExtValue(), I, ResType, TII);
2723-
return GR.getOrCreateConstInt(APInt(GR.getScalarOrVectorBitWidth(ResType), One.getZExtValue()), I, ResType, TII);
2729+
return GR.getOrCreateConstInt(
2730+
APInt(GR.getScalarOrVectorBitWidth(ResType), One.getZExtValue()), I,
2731+
ResType, TII);
27242732
}
27252733

27262734
bool SPIRVInstructionSelector::selectSelect(Register ResVReg,
@@ -2939,7 +2947,8 @@ bool SPIRVInstructionSelector::selectConst(Register ResVReg,
29392947
Reg = GR.getOrCreateConstFP(I.getOperand(1).getFPImm()->getValue(), I,
29402948
ResType, TII, !STI.isShader());
29412949
} else {
2942-
Reg = GR.getOrCreateConstInt(I.getOperand(1).getCImm()->getValue(), I, ResType, TII, !STI.isShader());
2950+
Reg = GR.getOrCreateConstInt(I.getOperand(1).getCImm()->getValue(), I,
2951+
ResType, TII, !STI.isShader());
29432952
}
29442953
return Reg == ResVReg ? true : BuildCOPY(ResVReg, Reg, I);
29452954
}
@@ -3764,7 +3773,8 @@ bool SPIRVInstructionSelector::selectFirstBitSet64Overflow(
37643773
bool ZeroAsNull = !STI.isShader();
37653774
Register FinalElemReg = MRI->createVirtualRegister(GR.getRegClass(I64Type));
37663775
Register ConstIntLastIdx = GR.getOrCreateConstInt(
3767-
APInt(GR.getScalarOrVectorBitWidth(BaseType), ComponentCount - 1), I, BaseType, TII, ZeroAsNull);
3776+
APInt(GR.getScalarOrVectorBitWidth(BaseType), ComponentCount - 1), I,
3777+
BaseType, TII, ZeroAsNull);
37683778

37693779
if (!selectOpWithSrcs(FinalElemReg, I64Type, I, {SrcReg, ConstIntLastIdx},
37703780
SPIRV::OpVectorExtractDynamic))
@@ -3793,9 +3803,11 @@ bool SPIRVInstructionSelector::selectFirstBitSet64(
37933803
SPIRVType *BaseType = GR.retrieveScalarOrVectorIntType(ResType);
37943804
bool ZeroAsNull = !STI.isShader();
37953805
Register ConstIntZero =
3796-
GR.getOrCreateConstInt(APInt(GR.getScalarOrVectorBitWidth(BaseType), 0), I, BaseType, TII, ZeroAsNull);
3806+
GR.getOrCreateConstInt(APInt(GR.getScalarOrVectorBitWidth(BaseType), 0),
3807+
I, BaseType, TII, ZeroAsNull);
37973808
Register ConstIntOne =
3798-
GR.getOrCreateConstInt(APInt(GR.getScalarOrVectorBitWidth(BaseType), 1), I, BaseType, TII, ZeroAsNull);
3809+
GR.getOrCreateConstInt(APInt(GR.getScalarOrVectorBitWidth(BaseType), 1),
3810+
I, BaseType, TII, ZeroAsNull);
37993811

38003812
// SPIRV doesn't support vectors with more than 4 components. Since the
38013813
// algoritm below converts i64 -> i32x2 and i64x4 -> i32x8 it can only
@@ -3879,10 +3891,15 @@ bool SPIRVInstructionSelector::selectFirstBitSet64(
38793891
unsigned AddOp;
38803892

38813893
if (IsScalarRes) {
3882-
NegOneReg =
3883-
GR.getOrCreateConstInt(APInt(GR.getScalarOrVectorBitWidth(ResType), (unsigned)-1), I, ResType, TII, ZeroAsNull);
3884-
Reg0 = GR.getOrCreateConstInt(APInt(GR.getScalarOrVectorBitWidth(ResType), 0), I, ResType, TII, ZeroAsNull);
3885-
Reg32 = GR.getOrCreateConstInt(APInt(GR.getScalarOrVectorBitWidth(ResType), 32), I, ResType, TII, ZeroAsNull);
3894+
NegOneReg = GR.getOrCreateConstInt(
3895+
APInt(GR.getScalarOrVectorBitWidth(ResType), (unsigned)-1), I, ResType,
3896+
TII, ZeroAsNull);
3897+
Reg0 =
3898+
GR.getOrCreateConstInt(APInt(GR.getScalarOrVectorBitWidth(ResType), 0),
3899+
I, ResType, TII, ZeroAsNull);
3900+
Reg32 =
3901+
GR.getOrCreateConstInt(APInt(GR.getScalarOrVectorBitWidth(ResType), 32),
3902+
I, ResType, TII, ZeroAsNull);
38863903
SelectOp = SPIRV::OpSelectSISCond;
38873904
AddOp = SPIRV::OpIAddS;
38883905
} else {

‎llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_arbitrary_precision_integers.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -54,4 +54,4 @@ define i160 @getConstantI160() {
5454

5555
; CHECK: %[[#GET_I160]] = OpFunction %[[#I160]]
5656
; CHECK: OpReturnValue %[[#CST_I160]]
57-
; CHECK: OpFunctionEnd
57+
; CHECK: OpFunctionEnd

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