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[AArch64] Add missing sForms to sForm
1 parent e87d775 commit fd92718

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7 files changed

+120
-112
lines changed

7 files changed

+120
-112
lines changed

‎llvm/lib/Target/AArch64/AArch64InstrInfo.cpp‎

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1730,12 +1730,20 @@ static unsigned sForm(MachineInstr &Instr) {
17301730

17311731
case AArch64::ADDSWrr:
17321732
case AArch64::ADDSWri:
1733+
case AArch64::ADDSWrx:
17331734
case AArch64::ADDSXrr:
17341735
case AArch64::ADDSXri:
1736+
case AArch64::ADDSXrx:
17351737
case AArch64::SUBSWrr:
17361738
case AArch64::SUBSWri:
1739+
case AArch64::SUBSWrx:
17371740
case AArch64::SUBSXrr:
17381741
case AArch64::SUBSXri:
1742+
case AArch64::SUBSXrx:
1743+
case AArch64::ADCSWr:
1744+
case AArch64::ADCSXr:
1745+
case AArch64::SBCSWr:
1746+
case AArch64::SBCSXr:
17391747
return Instr.getOpcode();
17401748

17411749
case AArch64::ADDWrr:
@@ -1746,6 +1754,10 @@ static unsigned sForm(MachineInstr &Instr) {
17461754
return AArch64::ADDSXrr;
17471755
case AArch64::ADDXri:
17481756
return AArch64::ADDSXri;
1757+
case AArch64::ADDWrx:
1758+
return AArch64::ADDSWrx;
1759+
case AArch64::ADDXrx:
1760+
return AArch64::ADDSXrx;
17491761
case AArch64::ADCWr:
17501762
return AArch64::ADCSWr;
17511763
case AArch64::ADCXr:
@@ -1758,6 +1770,10 @@ static unsigned sForm(MachineInstr &Instr) {
17581770
return AArch64::SUBSXrr;
17591771
case AArch64::SUBXri:
17601772
return AArch64::SUBSXri;
1773+
case AArch64::SUBWrx:
1774+
return AArch64::SUBSWrx;
1775+
case AArch64::SUBXrx:
1776+
return AArch64::SUBSXrx;
17611777
case AArch64::SBCWr:
17621778
return AArch64::SBCSWr;
17631779
case AArch64::SBCXr:

‎llvm/test/CodeGen/AArch64/abds-neg.ll‎

Lines changed: 5 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -9,8 +9,7 @@ define i8 @abd_ext_i8(i8 %a, i8 %b) nounwind {
99
; CHECK-LABEL: abd_ext_i8:
1010
; CHECK: // %bb.0:
1111
; CHECK-NEXT: sxtb w8, w0
12-
; CHECK-NEXT: sub w8, w8, w1, sxtb
13-
; CHECK-NEXT: cmp w8, #0
12+
; CHECK-NEXT: subs w8, w8, w1, sxtb
1413
; CHECK-NEXT: cneg w0, w8, pl
1514
; CHECK-NEXT: ret
1615
%aext = sext i8 %a to i64
@@ -26,8 +25,7 @@ define i8 @abd_ext_i8_i16(i8 %a, i16 %b) nounwind {
2625
; CHECK-LABEL: abd_ext_i8_i16:
2726
; CHECK: // %bb.0:
2827
; CHECK-NEXT: sxtb w8, w0
29-
; CHECK-NEXT: sub w8, w8, w1, sxth
30-
; CHECK-NEXT: cmp w8, #0
28+
; CHECK-NEXT: subs w8, w8, w1, sxth
3129
; CHECK-NEXT: cneg w0, w8, pl
3230
; CHECK-NEXT: ret
3331
%aext = sext i8 %a to i64
@@ -43,8 +41,7 @@ define i8 @abd_ext_i8_undef(i8 %a, i8 %b) nounwind {
4341
; CHECK-LABEL: abd_ext_i8_undef:
4442
; CHECK: // %bb.0:
4543
; CHECK-NEXT: sxtb w8, w0
46-
; CHECK-NEXT: sub w8, w8, w1, sxtb
47-
; CHECK-NEXT: cmp w8, #0
44+
; CHECK-NEXT: subs w8, w8, w1, sxtb
4845
; CHECK-NEXT: cneg w0, w8, pl
4946
; CHECK-NEXT: ret
5047
%aext = sext i8 %a to i64
@@ -60,8 +57,7 @@ define i16 @abd_ext_i16(i16 %a, i16 %b) nounwind {
6057
; CHECK-LABEL: abd_ext_i16:
6158
; CHECK: // %bb.0:
6259
; CHECK-NEXT: sxth w8, w0
63-
; CHECK-NEXT: sub w8, w8, w1, sxth
64-
; CHECK-NEXT: cmp w8, #0
60+
; CHECK-NEXT: subs w8, w8, w1, sxth
6561
; CHECK-NEXT: cneg w0, w8, pl
6662
; CHECK-NEXT: ret
6763
%aext = sext i16 %a to i64
@@ -93,8 +89,7 @@ define i16 @abd_ext_i16_undef(i16 %a, i16 %b) nounwind {
9389
; CHECK-LABEL: abd_ext_i16_undef:
9490
; CHECK: // %bb.0:
9591
; CHECK-NEXT: sxth w8, w0
96-
; CHECK-NEXT: sub w8, w8, w1, sxth
97-
; CHECK-NEXT: cmp w8, #0
92+
; CHECK-NEXT: subs w8, w8, w1, sxth
9893
; CHECK-NEXT: cneg w0, w8, pl
9994
; CHECK-NEXT: ret
10095
%aext = sext i16 %a to i64

‎llvm/test/CodeGen/AArch64/abds.ll‎

Lines changed: 11 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -9,8 +9,7 @@ define i8 @abd_ext_i8(i8 %a, i8 %b) nounwind {
99
; CHECK-LABEL: abd_ext_i8:
1010
; CHECK: // %bb.0:
1111
; CHECK-NEXT: sxtb w8, w0
12-
; CHECK-NEXT: sub w8, w8, w1, sxtb
13-
; CHECK-NEXT: cmp w8, #0
12+
; CHECK-NEXT: subs w8, w8, w1, sxtb
1413
; CHECK-NEXT: cneg w0, w8, mi
1514
; CHECK-NEXT: ret
1615
%aext = sext i8 %a to i64
@@ -25,8 +24,7 @@ define i8 @abd_ext_i8_i16(i8 %a, i16 %b) nounwind {
2524
; CHECK-LABEL: abd_ext_i8_i16:
2625
; CHECK: // %bb.0:
2726
; CHECK-NEXT: sxtb w8, w0
28-
; CHECK-NEXT: sub w8, w8, w1, sxth
29-
; CHECK-NEXT: cmp w8, #0
27+
; CHECK-NEXT: subs w8, w8, w1, sxth
3028
; CHECK-NEXT: cneg w0, w8, mi
3129
; CHECK-NEXT: ret
3230
%aext = sext i8 %a to i64
@@ -41,8 +39,7 @@ define i8 @abd_ext_i8_undef(i8 %a, i8 %b) nounwind {
4139
; CHECK-LABEL: abd_ext_i8_undef:
4240
; CHECK: // %bb.0:
4341
; CHECK-NEXT: sxtb w8, w0
44-
; CHECK-NEXT: sub w8, w8, w1, sxtb
45-
; CHECK-NEXT: cmp w8, #0
42+
; CHECK-NEXT: subs w8, w8, w1, sxtb
4643
; CHECK-NEXT: cneg w0, w8, mi
4744
; CHECK-NEXT: ret
4845
%aext = sext i8 %a to i64
@@ -57,8 +54,7 @@ define i16 @abd_ext_i16(i16 %a, i16 %b) nounwind {
5754
; CHECK-LABEL: abd_ext_i16:
5855
; CHECK: // %bb.0:
5956
; CHECK-NEXT: sxth w8, w0
60-
; CHECK-NEXT: sub w8, w8, w1, sxth
61-
; CHECK-NEXT: cmp w8, #0
57+
; CHECK-NEXT: subs w8, w8, w1, sxth
6258
; CHECK-NEXT: cneg w0, w8, mi
6359
; CHECK-NEXT: ret
6460
%aext = sext i16 %a to i64
@@ -88,8 +84,7 @@ define i16 @abd_ext_i16_undef(i16 %a, i16 %b) nounwind {
8884
; CHECK-LABEL: abd_ext_i16_undef:
8985
; CHECK: // %bb.0:
9086
; CHECK-NEXT: sxth w8, w0
91-
; CHECK-NEXT: sub w8, w8, w1, sxth
92-
; CHECK-NEXT: cmp w8, #0
87+
; CHECK-NEXT: subs w8, w8, w1, sxth
9388
; CHECK-NEXT: cneg w0, w8, mi
9489
; CHECK-NEXT: ret
9590
%aext = sext i16 %a to i64
@@ -214,8 +209,7 @@ define i8 @abd_minmax_i8(i8 %a, i8 %b) nounwind {
214209
; CHECK-LABEL: abd_minmax_i8:
215210
; CHECK: // %bb.0:
216211
; CHECK-NEXT: sxtb w8, w0
217-
; CHECK-NEXT: sub w8, w8, w1, sxtb
218-
; CHECK-NEXT: cmp w8, #0
212+
; CHECK-NEXT: subs w8, w8, w1, sxtb
219213
; CHECK-NEXT: cneg w0, w8, mi
220214
; CHECK-NEXT: ret
221215
%min = call i8 @llvm.smin.i8(i8 %a, i8 %b)
@@ -228,8 +222,7 @@ define i16 @abd_minmax_i16(i16 %a, i16 %b) nounwind {
228222
; CHECK-LABEL: abd_minmax_i16:
229223
; CHECK: // %bb.0:
230224
; CHECK-NEXT: sxth w8, w0
231-
; CHECK-NEXT: sub w8, w8, w1, sxth
232-
; CHECK-NEXT: cmp w8, #0
225+
; CHECK-NEXT: subs w8, w8, w1, sxth
233226
; CHECK-NEXT: cneg w0, w8, mi
234227
; CHECK-NEXT: ret
235228
%min = call i16 @llvm.smin.i16(i16 %a, i16 %b)
@@ -286,8 +279,7 @@ define i8 @abd_cmp_i8(i8 %a, i8 %b) nounwind {
286279
; CHECK-LABEL: abd_cmp_i8:
287280
; CHECK: // %bb.0:
288281
; CHECK-NEXT: sxtb w8, w0
289-
; CHECK-NEXT: sub w8, w8, w1, sxtb
290-
; CHECK-NEXT: cmp w8, #0
282+
; CHECK-NEXT: subs w8, w8, w1, sxtb
291283
; CHECK-NEXT: cneg w0, w8, mi
292284
; CHECK-NEXT: ret
293285
%cmp = icmp sgt i8 %a, %b
@@ -301,8 +293,7 @@ define i16 @abd_cmp_i16(i16 %a, i16 %b) nounwind {
301293
; CHECK-LABEL: abd_cmp_i16:
302294
; CHECK: // %bb.0:
303295
; CHECK-NEXT: sxth w8, w0
304-
; CHECK-NEXT: sub w8, w8, w1, sxth
305-
; CHECK-NEXT: cmp w8, #0
296+
; CHECK-NEXT: subs w8, w8, w1, sxth
306297
; CHECK-NEXT: cneg w0, w8, mi
307298
; CHECK-NEXT: ret
308299
%cmp = icmp sge i16 %a, %b
@@ -527,8 +518,7 @@ define i8 @abd_select_i8(i8 %a, i8 %b) nounwind {
527518
; CHECK-LABEL: abd_select_i8:
528519
; CHECK: // %bb.0:
529520
; CHECK-NEXT: sxtb w8, w0
530-
; CHECK-NEXT: sub w8, w8, w1, sxtb
531-
; CHECK-NEXT: cmp w8, #0
521+
; CHECK-NEXT: subs w8, w8, w1, sxtb
532522
; CHECK-NEXT: cneg w0, w8, mi
533523
; CHECK-NEXT: ret
534524
%cmp = icmp slt i8 %a, %b
@@ -542,8 +532,7 @@ define i16 @abd_select_i16(i16 %a, i16 %b) nounwind {
542532
; CHECK-LABEL: abd_select_i16:
543533
; CHECK: // %bb.0:
544534
; CHECK-NEXT: sxth w8, w0
545-
; CHECK-NEXT: sub w8, w8, w1, sxth
546-
; CHECK-NEXT: cmp w8, #0
535+
; CHECK-NEXT: subs w8, w8, w1, sxth
547536
; CHECK-NEXT: cneg w0, w8, mi
548537
; CHECK-NEXT: ret
549538
%cmp = icmp sle i16 %a, %b

‎llvm/test/CodeGen/AArch64/abdu-neg.ll‎

Lines changed: 5 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -9,8 +9,7 @@ define i8 @abd_ext_i8(i8 %a, i8 %b) nounwind {
99
; CHECK-LABEL: abd_ext_i8:
1010
; CHECK: // %bb.0:
1111
; CHECK-NEXT: and w8, w0, #0xff
12-
; CHECK-NEXT: sub w8, w8, w1, uxtb
13-
; CHECK-NEXT: cmp w8, #0
12+
; CHECK-NEXT: subs w8, w8, w1, uxtb
1413
; CHECK-NEXT: cneg w0, w8, pl
1514
; CHECK-NEXT: ret
1615
%aext = zext i8 %a to i64
@@ -26,8 +25,7 @@ define i8 @abd_ext_i8_i16(i8 %a, i16 %b) nounwind {
2625
; CHECK-LABEL: abd_ext_i8_i16:
2726
; CHECK: // %bb.0:
2827
; CHECK-NEXT: and w8, w0, #0xff
29-
; CHECK-NEXT: sub w8, w8, w1, uxth
30-
; CHECK-NEXT: cmp w8, #0
28+
; CHECK-NEXT: subs w8, w8, w1, uxth
3129
; CHECK-NEXT: cneg w0, w8, pl
3230
; CHECK-NEXT: ret
3331
%aext = zext i8 %a to i64
@@ -43,8 +41,7 @@ define i8 @abd_ext_i8_undef(i8 %a, i8 %b) nounwind {
4341
; CHECK-LABEL: abd_ext_i8_undef:
4442
; CHECK: // %bb.0:
4543
; CHECK-NEXT: and w8, w0, #0xff
46-
; CHECK-NEXT: sub w8, w8, w1, uxtb
47-
; CHECK-NEXT: cmp w8, #0
44+
; CHECK-NEXT: subs w8, w8, w1, uxtb
4845
; CHECK-NEXT: cneg w0, w8, pl
4946
; CHECK-NEXT: ret
5047
%aext = zext i8 %a to i64
@@ -60,8 +57,7 @@ define i16 @abd_ext_i16(i16 %a, i16 %b) nounwind {
6057
; CHECK-LABEL: abd_ext_i16:
6158
; CHECK: // %bb.0:
6259
; CHECK-NEXT: and w8, w0, #0xffff
63-
; CHECK-NEXT: sub w8, w8, w1, uxth
64-
; CHECK-NEXT: cmp w8, #0
60+
; CHECK-NEXT: subs w8, w8, w1, uxth
6561
; CHECK-NEXT: cneg w0, w8, pl
6662
; CHECK-NEXT: ret
6763
%aext = zext i16 %a to i64
@@ -93,8 +89,7 @@ define i16 @abd_ext_i16_undef(i16 %a, i16 %b) nounwind {
9389
; CHECK-LABEL: abd_ext_i16_undef:
9490
; CHECK: // %bb.0:
9591
; CHECK-NEXT: and w8, w0, #0xffff
96-
; CHECK-NEXT: sub w8, w8, w1, uxth
97-
; CHECK-NEXT: cmp w8, #0
92+
; CHECK-NEXT: subs w8, w8, w1, uxth
9893
; CHECK-NEXT: cneg w0, w8, pl
9994
; CHECK-NEXT: ret
10095
%aext = zext i16 %a to i64

‎llvm/test/CodeGen/AArch64/abdu.ll‎

Lines changed: 11 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -9,8 +9,7 @@ define i8 @abd_ext_i8(i8 %a, i8 %b) nounwind {
99
; CHECK-LABEL: abd_ext_i8:
1010
; CHECK: // %bb.0:
1111
; CHECK-NEXT: and w8, w0, #0xff
12-
; CHECK-NEXT: sub w8, w8, w1, uxtb
13-
; CHECK-NEXT: cmp w8, #0
12+
; CHECK-NEXT: subs w8, w8, w1, uxtb
1413
; CHECK-NEXT: cneg w0, w8, mi
1514
; CHECK-NEXT: ret
1615
%aext = zext i8 %a to i64
@@ -25,8 +24,7 @@ define i8 @abd_ext_i8_i16(i8 %a, i16 %b) nounwind {
2524
; CHECK-LABEL: abd_ext_i8_i16:
2625
; CHECK: // %bb.0:
2726
; CHECK-NEXT: and w8, w0, #0xff
28-
; CHECK-NEXT: sub w8, w8, w1, uxth
29-
; CHECK-NEXT: cmp w8, #0
27+
; CHECK-NEXT: subs w8, w8, w1, uxth
3028
; CHECK-NEXT: cneg w0, w8, mi
3129
; CHECK-NEXT: ret
3230
%aext = zext i8 %a to i64
@@ -41,8 +39,7 @@ define i8 @abd_ext_i8_undef(i8 %a, i8 %b) nounwind {
4139
; CHECK-LABEL: abd_ext_i8_undef:
4240
; CHECK: // %bb.0:
4341
; CHECK-NEXT: and w8, w0, #0xff
44-
; CHECK-NEXT: sub w8, w8, w1, uxtb
45-
; CHECK-NEXT: cmp w8, #0
42+
; CHECK-NEXT: subs w8, w8, w1, uxtb
4643
; CHECK-NEXT: cneg w0, w8, mi
4744
; CHECK-NEXT: ret
4845
%aext = zext i8 %a to i64
@@ -57,8 +54,7 @@ define i16 @abd_ext_i16(i16 %a, i16 %b) nounwind {
5754
; CHECK-LABEL: abd_ext_i16:
5855
; CHECK: // %bb.0:
5956
; CHECK-NEXT: and w8, w0, #0xffff
60-
; CHECK-NEXT: sub w8, w8, w1, uxth
61-
; CHECK-NEXT: cmp w8, #0
57+
; CHECK-NEXT: subs w8, w8, w1, uxth
6258
; CHECK-NEXT: cneg w0, w8, mi
6359
; CHECK-NEXT: ret
6460
%aext = zext i16 %a to i64
@@ -88,8 +84,7 @@ define i16 @abd_ext_i16_undef(i16 %a, i16 %b) nounwind {
8884
; CHECK-LABEL: abd_ext_i16_undef:
8985
; CHECK: // %bb.0:
9086
; CHECK-NEXT: and w8, w0, #0xffff
91-
; CHECK-NEXT: sub w8, w8, w1, uxth
92-
; CHECK-NEXT: cmp w8, #0
87+
; CHECK-NEXT: subs w8, w8, w1, uxth
9388
; CHECK-NEXT: cneg w0, w8, mi
9489
; CHECK-NEXT: ret
9590
%aext = zext i16 %a to i64
@@ -218,8 +213,7 @@ define i8 @abd_minmax_i8(i8 %a, i8 %b) nounwind {
218213
; CHECK-LABEL: abd_minmax_i8:
219214
; CHECK: // %bb.0:
220215
; CHECK-NEXT: and w8, w0, #0xff
221-
; CHECK-NEXT: sub w8, w8, w1, uxtb
222-
; CHECK-NEXT: cmp w8, #0
216+
; CHECK-NEXT: subs w8, w8, w1, uxtb
223217
; CHECK-NEXT: cneg w0, w8, mi
224218
; CHECK-NEXT: ret
225219
%min = call i8 @llvm.umin.i8(i8 %a, i8 %b)
@@ -232,8 +226,7 @@ define i16 @abd_minmax_i16(i16 %a, i16 %b) nounwind {
232226
; CHECK-LABEL: abd_minmax_i16:
233227
; CHECK: // %bb.0:
234228
; CHECK-NEXT: and w8, w0, #0xffff
235-
; CHECK-NEXT: sub w8, w8, w1, uxth
236-
; CHECK-NEXT: cmp w8, #0
229+
; CHECK-NEXT: subs w8, w8, w1, uxth
237230
; CHECK-NEXT: cneg w0, w8, mi
238231
; CHECK-NEXT: ret
239232
%min = call i16 @llvm.umin.i16(i16 %a, i16 %b)
@@ -292,8 +285,7 @@ define i8 @abd_cmp_i8(i8 %a, i8 %b) nounwind {
292285
; CHECK-LABEL: abd_cmp_i8:
293286
; CHECK: // %bb.0:
294287
; CHECK-NEXT: and w8, w0, #0xff
295-
; CHECK-NEXT: sub w8, w8, w1, uxtb
296-
; CHECK-NEXT: cmp w8, #0
288+
; CHECK-NEXT: subs w8, w8, w1, uxtb
297289
; CHECK-NEXT: cneg w0, w8, mi
298290
; CHECK-NEXT: ret
299291
%cmp = icmp ugt i8 %a, %b
@@ -307,8 +299,7 @@ define i16 @abd_cmp_i16(i16 %a, i16 %b) nounwind {
307299
; CHECK-LABEL: abd_cmp_i16:
308300
; CHECK: // %bb.0:
309301
; CHECK-NEXT: and w8, w0, #0xffff
310-
; CHECK-NEXT: sub w8, w8, w1, uxth
311-
; CHECK-NEXT: cmp w8, #0
302+
; CHECK-NEXT: subs w8, w8, w1, uxth
312303
; CHECK-NEXT: cneg w0, w8, mi
313304
; CHECK-NEXT: ret
314305
%cmp = icmp uge i16 %a, %b
@@ -392,8 +383,7 @@ define i8 @abd_select_i8(i8 %a, i8 %b) nounwind {
392383
; CHECK-LABEL: abd_select_i8:
393384
; CHECK: // %bb.0:
394385
; CHECK-NEXT: and w8, w0, #0xff
395-
; CHECK-NEXT: sub w8, w8, w1, uxtb
396-
; CHECK-NEXT: cmp w8, #0
386+
; CHECK-NEXT: subs w8, w8, w1, uxtb
397387
; CHECK-NEXT: cneg w0, w8, mi
398388
; CHECK-NEXT: ret
399389
%cmp = icmp ult i8 %a, %b
@@ -407,8 +397,7 @@ define i16 @abd_select_i16(i16 %a, i16 %b) nounwind {
407397
; CHECK-LABEL: abd_select_i16:
408398
; CHECK: // %bb.0:
409399
; CHECK-NEXT: and w8, w0, #0xffff
410-
; CHECK-NEXT: sub w8, w8, w1, uxth
411-
; CHECK-NEXT: cmp w8, #0
400+
; CHECK-NEXT: subs w8, w8, w1, uxth
412401
; CHECK-NEXT: cneg w0, w8, mi
413402
; CHECK-NEXT: ret
414403
%cmp = icmp ule i16 %a, %b

‎llvm/test/CodeGen/AArch64/abs.ll‎

Lines changed: 30 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -388,3 +388,33 @@ entry:
388388
ret <3 x i32> %res
389389
}
390390
declare <3 x i32> @llvm.abs.v3i32(<3 x i32>, i1)
391+
392+
define i32 @combine_subs_multiple_sub_uses(i32 %a, i32 %b) {
393+
; CHECK-LABEL: combine_subs_multiple_sub_uses:
394+
; CHECK: // %bb.0:
395+
; CHECK-NEXT: subs w8, w0, w1
396+
; CHECK-NEXT: csel w9, w0, w1, ne
397+
; CHECK-NEXT: add w0, w9, w8
398+
; CHECK-NEXT: ret
399+
%sub = sub i32 %a, %b
400+
%cc = icmp ne i32 %sub, 0
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%sel = select i1 %cc, i32 %a, i32 %b
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%add = add i32 %sel, %sub
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ret i32 %add
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}
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define i32 @do_not_combine_subs_multiple_flag_uses(i32 %a, i32 %b, i32 %c, i32 %d) {
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; CHECK-LABEL: do_not_combine_subs_multiple_flag_uses:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp w0, w1
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; CHECK-NEXT: csel w8, w0, w1, ne
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; CHECK-NEXT: csel w9, w2, w3, ne
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; CHECK-NEXT: add w0, w8, w9
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; CHECK-NEXT: ret
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%sub = sub i32 %a, %b
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%cc = icmp ne i32 %sub, 0
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%sel = select i1 %cc, i32 %a, i32 %b
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%other = select i1 %cc, i32 %c, i32 %d
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%add = add i32 %sel, %other
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ret i32 %add
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}

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