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kazutakahiratakazutakahirata
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[ARM] Remove unnecessary casts (NFC)
Decoder is already of const MCDisassembler *.
1 parent 1db33f1 commit fe1fb16

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‎llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp‎

Lines changed: 19 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -877,8 +877,7 @@ static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
877877
/// is an address into a section with 'C' string literals.
878878
static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
879879
const MCDisassembler *Decoder) {
880-
const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
881-
Dis->tryAddingPcLoadReferenceComment(Value, Address);
880+
Decoder->tryAddingPcLoadReferenceComment(Value, Address);
882881
}
883882

884883
// Thumb1 instructions don't have explicit S bits. Rather, they
@@ -1482,7 +1481,7 @@ static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
14821481
DecodeStatus S = MCDisassembler::Success;
14831482

14841483
const FeatureBitset &featureBits =
1485-
((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1484+
Decoder->getSubtargetInfo().getFeatureBits();
14861485

14871486
if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15)
14881487
S = MCDisassembler::SoftFail;
@@ -1535,7 +1534,7 @@ static bool PermitsD32(const MCInst &Inst, const MCDisassembler *Decoder) {
15351534
if (Inst.getOpcode() == ARM::VSCCLRMD || Inst.getOpcode() == ARM::VSCCLRMS)
15361535
return true;
15371536
const FeatureBitset &featureBits =
1538-
((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1537+
Decoder->getSubtargetInfo().getFeatureBits();
15391538
return featureBits[ARM::FeatureD32];
15401539
}
15411540

@@ -1879,7 +1878,7 @@ static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
18791878
unsigned Rn = fieldFromInstruction(Insn, 16, 4);
18801879
unsigned U = fieldFromInstruction(Insn, 23, 1);
18811880
const FeatureBitset &featureBits =
1882-
((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1881+
Decoder->getSubtargetInfo().getFeatureBits();
18831882

18841883
switch (Inst.getOpcode()) {
18851884
case ARM::LDC_OFFSET:
@@ -2553,8 +2552,8 @@ static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
25532552
const MCDisassembler *Decoder) {
25542553
unsigned pred = fieldFromInstruction(Insn, 28, 4);
25552554
unsigned imm8 = fieldFromInstruction(Insn, 0, 8);
2556-
const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
2557-
const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
2555+
const FeatureBitset &FeatureBits =
2556+
Decoder->getSubtargetInfo().getFeatureBits();
25582557

25592558
DecodeStatus S = MCDisassembler::Success;
25602559

@@ -2798,8 +2797,8 @@ static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
27982797

27992798
unsigned Imm = fieldFromInstruction(Insn, 9, 1);
28002799

2801-
const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
2802-
const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
2800+
const FeatureBitset &FeatureBits =
2801+
Decoder->getSubtargetInfo().getFeatureBits();
28032802

28042803
if (!FeatureBits[ARM::HasV8_1aOps] ||
28052804
!FeatureBits[ARM::HasV8Ops])
@@ -4081,7 +4080,7 @@ static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
40814080
unsigned Rn = fieldFromInstruction(Insn, 16, 4);
40824081

40834082
const FeatureBitset &featureBits =
4084-
((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4083+
Decoder->getSubtargetInfo().getFeatureBits();
40854084

40864085
bool hasMP = featureBits[ARM::FeatureMP];
40874086
bool hasV7Ops = featureBits[ARM::HasV7Ops];
@@ -4170,7 +4169,7 @@ static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
41704169
unsigned add = fieldFromInstruction(Insn, 9, 1);
41714170

41724171
const FeatureBitset &featureBits =
4173-
((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4172+
Decoder->getSubtargetInfo().getFeatureBits();
41744173

41754174
bool hasMP = featureBits[ARM::FeatureMP];
41764175
bool hasV7Ops = featureBits[ARM::HasV7Ops];
@@ -4252,7 +4251,7 @@ static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
42524251
imm |= (Rn << 13);
42534252

42544253
const FeatureBitset &featureBits =
4255-
((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4254+
Decoder->getSubtargetInfo().getFeatureBits();
42564255

42574256
bool hasMP = featureBits[ARM::FeatureMP];
42584257
bool hasV7Ops = featureBits[ARM::HasV7Ops];
@@ -4371,7 +4370,7 @@ static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
43714370
int imm = fieldFromInstruction(Insn, 0, 12);
43724371

43734372
const FeatureBitset &featureBits =
4374-
((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4373+
Decoder->getSubtargetInfo().getFeatureBits();
43754374

43764375
bool hasV7Ops = featureBits[ARM::HasV7Ops];
43774376

@@ -4826,7 +4825,7 @@ static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
48264825
return MCDisassembler::Fail;
48274826

48284827
const FeatureBitset &featureBits =
4829-
((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4828+
Decoder->getSubtargetInfo().getFeatureBits();
48304829

48314830
if (!isValidCoprocessorNumber(Val, featureBits))
48324831
return MCDisassembler::Fail;
@@ -4839,7 +4838,7 @@ static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
48394838
uint64_t Address,
48404839
const MCDisassembler *Decoder) {
48414840
const FeatureBitset &FeatureBits =
4842-
((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4841+
Decoder->getSubtargetInfo().getFeatureBits();
48434842
DecodeStatus S = MCDisassembler::Success;
48444843

48454844
unsigned Rn = fieldFromInstruction(Insn, 16, 4);
@@ -4984,7 +4983,7 @@ static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, uint64_t Address,
49844983
const MCDisassembler *Decoder) {
49854984
DecodeStatus S = MCDisassembler::Success;
49864985
const FeatureBitset &FeatureBits =
4987-
((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4986+
Decoder->getSubtargetInfo().getFeatureBits();
49884987

49894988
if (FeatureBits[ARM::FeatureMClass]) {
49904989
unsigned ValLow = Val & 0xff;
@@ -6019,7 +6018,7 @@ static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address,
60196018
static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address,
60206019
const MCDisassembler *Decoder) {
60216020
const FeatureBitset &featureBits =
6022-
((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
6021+
Decoder->getSubtargetInfo().getFeatureBits();
60236022
bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
60246023

60256024
unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
@@ -6078,7 +6077,7 @@ static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address,
60786077
static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, uint64_t Address,
60796078
const MCDisassembler *Decoder) {
60806079
const FeatureBitset &featureBits =
6081-
((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
6080+
Decoder->getSubtargetInfo().getFeatureBits();
60826081
bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
60836082

60846083
unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
@@ -6244,7 +6243,7 @@ static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,
62446243
uint64_t Address,
62456244
const MCDisassembler *Decoder) {
62466245
const FeatureBitset &featureBits =
6247-
((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
6246+
Decoder->getSubtargetInfo().getFeatureBits();
62486247
DecodeStatus S = MCDisassembler::Success;
62496248

62506249
// Add explicit operand for the destination sysreg, for cases where
@@ -6717,7 +6716,7 @@ static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Val,
67176716
case ARM::VLDR_FPSCR_post:
67186717
case ARM::VLDR_FPSCR_NZCVQC_post:
67196718
const FeatureBitset &featureBits =
6720-
((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
6719+
Decoder->getSubtargetInfo().getFeatureBits();
67216720

67226721
if (!featureBits[ARM::HasMVEIntegerOps] && !featureBits[ARM::FeatureVFP2])
67236722
return MCDisassembler::Fail;

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