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RKSimontru
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[DAG] MatchRotate - bail if we fail to match a shl/srl pair
extractShiftForRotate may fail to return canonicalized shifts due to constant folding or other simplification that can occur in getNode() Fixes Issue #57283 (cherry picked from commit e624f8a)
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llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

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@@ -7574,6 +7574,10 @@ SDValue DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, const SDLoc &DL) {
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std::swap(LHSMask, RHSMask);
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}
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// Something has gone wrong - we've lost the shl/srl pair - bail.
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if (LHSShift.getOpcode() != ISD::SHL || RHSShift.getOpcode() != ISD::SRL)
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return SDValue();
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unsigned EltSizeInBits = VT.getScalarSizeInBits();
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SDValue LHSShiftArg = LHSShift.getOperand(0);
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SDValue LHSShiftAmt = LHSShift.getOperand(1);

llvm/test/CodeGen/X86/pr57283.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown | FileCheck %s --check-prefix=X86
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; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s --check-prefix=X64
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define void @PR57283() nounwind {
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; X86-LABEL: PR57283:
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; X86: # %bb.0: # %BB
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; X86-NEXT: pushl %ebp
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; X86-NEXT: movl %esp, %ebp
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; X86-NEXT: andl $-8, %esp
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; X86-NEXT: subl $16, %esp
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; X86-NEXT: movl $0, {{[0-9]+}}(%esp)
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; X86-NEXT: movl $0, (%esp)
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; X86-NEXT: movl $0, {{[0-9]+}}(%esp)
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; X86-NEXT: movl $0, {{[0-9]+}}(%esp)
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; X86-NEXT: movl %ebp, %esp
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; X86-NEXT: popl %ebp
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; X86-NEXT: retl
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;
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; X64-LABEL: PR57283:
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; X64: # %bb.0: # %BB
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; X64-NEXT: movq $0, -{{[0-9]+}}(%rsp)
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; X64-NEXT: movq $0, -{{[0-9]+}}(%rsp)
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; X64-NEXT: retq
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BB:
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%A6 = alloca i64, align 8
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%A = alloca i64, align 8
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%L = load i64, i64* %A, align 4
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%B3 = sub i64 %L, %L
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%B2 = mul i64 %B3, 4294967296
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%B1 = add i64 %B2, %B2
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%B4 = udiv i64 %B2, -9223372036854775808
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%B = xor i64 %B1, %B4
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store i64 %B, i64* %A, align 4
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%B5 = sdiv i64 %B, -1
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store i64 %B5, i64* %A6, align 4
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ret void
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}

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