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michaelmaitlandmichaelmaitland
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fixup! update tests
1 parent 595a709 commit fe55f64

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3 files changed

+1
-25
lines changed

3 files changed

+1
-25
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‎llvm/test/CodeGen/RISCV/double_reduct.ll‎

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -133,11 +133,8 @@ define i32 @mul_i32(<4 x i32> %a, <4 x i32> %b) {
133133
; RV32-NEXT: vslidedown.vi v10, v9, 2
134134
; RV32-NEXT: vmul.vv v9, v9, v10
135135
; RV32-NEXT: vrgather.vi v10, v8, 1
136-
; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
137136
; RV32-NEXT: vmul.vv v8, v8, v10
138-
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
139137
; RV32-NEXT: vrgather.vi v10, v9, 1
140-
; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
141138
; RV32-NEXT: vmul.vv v9, v9, v10
142139
; RV32-NEXT: vmv.x.s a0, v8
143140
; RV32-NEXT: vmv.x.s a1, v9
@@ -152,11 +149,8 @@ define i32 @mul_i32(<4 x i32> %a, <4 x i32> %b) {
152149
; RV64-NEXT: vslidedown.vi v10, v9, 2
153150
; RV64-NEXT: vmul.vv v9, v9, v10
154151
; RV64-NEXT: vrgather.vi v10, v8, 1
155-
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
156152
; RV64-NEXT: vmul.vv v8, v8, v10
157-
; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
158153
; RV64-NEXT: vrgather.vi v10, v9, 1
159-
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
160154
; RV64-NEXT: vmul.vv v9, v9, v10
161155
; RV64-NEXT: vmv.x.s a0, v8
162156
; RV64-NEXT: vmv.x.s a1, v9

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll‎

Lines changed: 0 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1456,7 +1456,6 @@ define signext i8 @vpreduce_mul_v2i8(i8 signext %s, <2 x i8> %v, <2 x i1> %m, i3
14561456
; RV32-NEXT: vmv.v.i v9, 1
14571457
; RV32-NEXT: vmerge.vvm v8, v9, v8, v0
14581458
; RV32-NEXT: vrgather.vi v9, v8, 1
1459-
; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
14601459
; RV32-NEXT: vmul.vv v8, v8, v9
14611460
; RV32-NEXT: vmv.x.s a0, v8
14621461
; RV32-NEXT: mv a1, a2
@@ -1484,7 +1483,6 @@ define signext i8 @vpreduce_mul_v2i8(i8 signext %s, <2 x i8> %v, <2 x i1> %m, i3
14841483
; RV64-NEXT: vmv.v.i v9, 1
14851484
; RV64-NEXT: vmerge.vvm v8, v9, v8, v0
14861485
; RV64-NEXT: vrgather.vi v9, v8, 1
1487-
; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
14881486
; RV64-NEXT: vmul.vv v8, v8, v9
14891487
; RV64-NEXT: vmv.x.s a0, v8
14901488
; RV64-NEXT: mv a1, a2
@@ -1520,7 +1518,6 @@ define signext i8 @vpreduce_mul_v4i8(i8 signext %s, <4 x i8> %v, <4 x i1> %m, i3
15201518
; RV32-NEXT: vslidedown.vi v9, v8, 2
15211519
; RV32-NEXT: vmul.vv v8, v8, v9
15221520
; RV32-NEXT: vrgather.vi v9, v8, 1
1523-
; RV32-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
15241521
; RV32-NEXT: vmul.vv v8, v8, v9
15251522
; RV32-NEXT: vmv.x.s a0, v8
15261523
; RV32-NEXT: mv a1, a2
@@ -1550,7 +1547,6 @@ define signext i8 @vpreduce_mul_v4i8(i8 signext %s, <4 x i8> %v, <4 x i1> %m, i3
15501547
; RV64-NEXT: vslidedown.vi v9, v8, 2
15511548
; RV64-NEXT: vmul.vv v8, v8, v9
15521549
; RV64-NEXT: vrgather.vi v9, v8, 1
1553-
; RV64-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
15541550
; RV64-NEXT: vmul.vv v8, v8, v9
15551551
; RV64-NEXT: vmv.x.s a0, v8
15561552
; RV64-NEXT: mv a1, a2
@@ -1588,7 +1584,6 @@ define signext i8 @vpreduce_mul_v8i8(i8 signext %s, <8 x i8> %v, <8 x i1> %m, i3
15881584
; RV32-NEXT: vslidedown.vi v9, v8, 2
15891585
; RV32-NEXT: vmul.vv v8, v8, v9
15901586
; RV32-NEXT: vrgather.vi v9, v8, 1
1591-
; RV32-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
15921587
; RV32-NEXT: vmul.vv v8, v8, v9
15931588
; RV32-NEXT: vmv.x.s a0, v8
15941589
; RV32-NEXT: mv a1, a2
@@ -1620,7 +1615,6 @@ define signext i8 @vpreduce_mul_v8i8(i8 signext %s, <8 x i8> %v, <8 x i1> %m, i3
16201615
; RV64-NEXT: vslidedown.vi v9, v8, 2
16211616
; RV64-NEXT: vmul.vv v8, v8, v9
16221617
; RV64-NEXT: vrgather.vi v9, v8, 1
1623-
; RV64-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
16241618
; RV64-NEXT: vmul.vv v8, v8, v9
16251619
; RV64-NEXT: vmv.x.s a0, v8
16261620
; RV64-NEXT: mv a1, a2
@@ -1660,7 +1654,6 @@ define signext i8 @vpreduce_mul_v16i8(i8 signext %s, <16 x i8> %v, <16 x i1> %m,
16601654
; RV32-NEXT: vslidedown.vi v9, v8, 2
16611655
; RV32-NEXT: vmul.vv v8, v8, v9
16621656
; RV32-NEXT: vrgather.vi v9, v8, 1
1663-
; RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma
16641657
; RV32-NEXT: vmul.vv v8, v8, v9
16651658
; RV32-NEXT: vmv.x.s a0, v8
16661659
; RV32-NEXT: mv a1, a2
@@ -1694,7 +1687,6 @@ define signext i8 @vpreduce_mul_v16i8(i8 signext %s, <16 x i8> %v, <16 x i1> %m,
16941687
; RV64-NEXT: vslidedown.vi v9, v8, 2
16951688
; RV64-NEXT: vmul.vv v8, v8, v9
16961689
; RV64-NEXT: vrgather.vi v9, v8, 1
1697-
; RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma
16981690
; RV64-NEXT: vmul.vv v8, v8, v9
16991691
; RV64-NEXT: vmv.x.s a0, v8
17001692
; RV64-NEXT: mv a1, a2

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll‎

Lines changed: 1 addition & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -5935,7 +5935,6 @@ define i8 @vreduce_mul_v2i8(ptr %x) {
59355935
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
59365936
; CHECK-NEXT: vle8.v v8, (a0)
59375937
; CHECK-NEXT: lbu a0, 1(a0)
5938-
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
59395938
; CHECK-NEXT: vmul.vx v8, v8, a0
59405939
; CHECK-NEXT: vmv.x.s a0, v8
59415940
; CHECK-NEXT: ret
@@ -5978,7 +5977,6 @@ define i8 @vreduce_mul_v4i8(ptr %x) {
59785977
; CHECK-NEXT: vslidedown.vi v9, v8, 2
59795978
; CHECK-NEXT: vmul.vv v8, v8, v9
59805979
; CHECK-NEXT: vrgather.vi v9, v8, 1
5981-
; CHECK-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
59825980
; CHECK-NEXT: vmul.vv v8, v8, v9
59835981
; CHECK-NEXT: vmv.x.s a0, v8
59845982
; CHECK-NEXT: ret
@@ -5999,7 +5997,6 @@ define i8 @vreduce_mul_v8i8(ptr %x) {
59995997
; CHECK-NEXT: vslidedown.vi v9, v8, 2
60005998
; CHECK-NEXT: vmul.vv v8, v8, v9
60015999
; CHECK-NEXT: vrgather.vi v9, v8, 1
6002-
; CHECK-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
60036000
; CHECK-NEXT: vmul.vv v8, v8, v9
60046001
; CHECK-NEXT: vmv.x.s a0, v8
60056002
; CHECK-NEXT: ret
@@ -6022,7 +6019,6 @@ define i8 @vreduce_mul_v16i8(ptr %x) {
60226019
; CHECK-NEXT: vslidedown.vi v9, v8, 2
60236020
; CHECK-NEXT: vmul.vv v8, v8, v9
60246021
; CHECK-NEXT: vrgather.vi v9, v8, 1
6025-
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
60266022
; CHECK-NEXT: vmul.vv v8, v8, v9
60276023
; CHECK-NEXT: vmv.x.s a0, v8
60286024
; CHECK-NEXT: ret
@@ -6171,7 +6167,6 @@ define i16 @vreduce_mul_v2i16(ptr %x) {
61716167
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
61726168
; CHECK-NEXT: vle16.v v8, (a0)
61736169
; CHECK-NEXT: lh a0, 2(a0)
6174-
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
61756170
; CHECK-NEXT: vmul.vx v8, v8, a0
61766171
; CHECK-NEXT: vmv.x.s a0, v8
61776172
; CHECK-NEXT: ret
@@ -6190,7 +6185,6 @@ define i16 @vreduce_mul_v4i16(ptr %x) {
61906185
; CHECK-NEXT: vslidedown.vi v9, v8, 2
61916186
; CHECK-NEXT: vmul.vv v8, v8, v9
61926187
; CHECK-NEXT: vrgather.vi v9, v8, 1
6193-
; CHECK-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
61946188
; CHECK-NEXT: vmul.vv v8, v8, v9
61956189
; CHECK-NEXT: vmv.x.s a0, v8
61966190
; CHECK-NEXT: ret
@@ -6211,7 +6205,6 @@ define i16 @vreduce_mul_v8i16(ptr %x) {
62116205
; CHECK-NEXT: vslidedown.vi v9, v8, 2
62126206
; CHECK-NEXT: vmul.vv v8, v8, v9
62136207
; CHECK-NEXT: vrgather.vi v9, v8, 1
6214-
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
62156208
; CHECK-NEXT: vmul.vv v8, v8, v9
62166209
; CHECK-NEXT: vmv.x.s a0, v8
62176210
; CHECK-NEXT: ret
@@ -6348,7 +6341,6 @@ define i32 @vreduce_mul_v2i32(ptr %x) {
63486341
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
63496342
; CHECK-NEXT: vle32.v v8, (a0)
63506343
; CHECK-NEXT: lw a0, 4(a0)
6351-
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
63526344
; CHECK-NEXT: vmul.vx v8, v8, a0
63536345
; CHECK-NEXT: vmv.x.s a0, v8
63546346
; CHECK-NEXT: ret
@@ -6367,7 +6359,6 @@ define i32 @vreduce_mul_v4i32(ptr %x) {
63676359
; CHECK-NEXT: vslidedown.vi v9, v8, 2
63686360
; CHECK-NEXT: vmul.vv v8, v8, v9
63696361
; CHECK-NEXT: vrgather.vi v9, v8, 1
6370-
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
63716362
; CHECK-NEXT: vmul.vv v8, v8, v9
63726363
; CHECK-NEXT: vmv.x.s a0, v8
63736364
; CHECK-NEXT: ret
@@ -6505,9 +6496,9 @@ define i64 @vreduce_mul_v2i64(ptr %x) {
65056496
; RV32-NEXT: addi a0, a0, 8
65066497
; RV32-NEXT: vlse64.v v9, (a0), zero
65076498
; RV32-NEXT: li a1, 32
6508-
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
65096499
; RV32-NEXT: vmul.vv v8, v8, v9
65106500
; RV32-NEXT: vmv.x.s a0, v8
6501+
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
65116502
; RV32-NEXT: vsrl.vx v8, v8, a1
65126503
; RV32-NEXT: vmv.x.s a1, v8
65136504
; RV32-NEXT: ret
@@ -6517,7 +6508,6 @@ define i64 @vreduce_mul_v2i64(ptr %x) {
65176508
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
65186509
; RV64-NEXT: vle64.v v8, (a0)
65196510
; RV64-NEXT: ld a0, 8(a0)
6520-
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
65216511
; RV64-NEXT: vmul.vx v8, v8, a0
65226512
; RV64-NEXT: vmv.x.s a0, v8
65236513
; RV64-NEXT: ret

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